diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2015-09-22 13:33:56 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-02-21 18:55:58 -0800 |
| commit | 0cd6138ddc88ac5eee8e13ec65f49442b349cc8e (patch) | |
| tree | 7e7519e81300c62c09d9467d24f9848de99b12a1 | |
| parent | 0c2a7c38f3b6015dfd4d7564c3c449cd70b80940 (diff) | |
Tegra: enable processor retention and L2/CPUECTLR access
This patch enables the processor retention and L2/CPUECTLR read/write
access from the NS world only for Cortex-A57 CPUs on the Tegra SoCs.
Change-Id: I9941a67686ea149cb95d80716fa1d03645325445
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| -rw-r--r-- | plat/nvidia/tegra/common/aarch64/tegra_helpers.S | 36 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/t210/tegra_def.h | 14 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t210/platform_t210.mk | 9 |
3 files changed, 29 insertions, 30 deletions
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index 905c4c5f..0474cc1a 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -35,6 +35,22 @@ #include <cortex_a53.h> #include <tegra_def.h> +#define MIDR_PN_CORTEX_A57 0xD07 + +/******************************************************************************* + * Implementation defined ACTLR_EL3 bit definitions + ******************************************************************************/ +#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) +#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) +#define ACTLR_EL3_L2CTLR_BIT (1 << 4) +#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) +#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) +#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ + ACTLR_EL3_L2ECTLR_BIT | \ + ACTLR_EL3_L2CTLR_BIT | \ + ACTLR_EL3_CPUECTLR_BIT | \ + ACTLR_EL3_CPUACTLR_BIT) + /* Global functions */ .globl plat_is_my_cpu_primary .globl plat_my_core_pos @@ -57,7 +73,18 @@ */ .macro cpu_init_common -#if ENABLE_L2_DYNAMIC_RETENTION + /* ------------------------------------------------ + * We enable procesor retention and L2/CPUECTLR NS + * access for A57 CPUs only. + * ------------------------------------------------ + */ + mrs x0, midr_el1 + mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) + and x0, x0, x1 + lsr x0, x0, #MIDR_PN_SHIFT + cmp x0, #MIDR_PN_CORTEX_A57 + b.ne 1f + /* --------------------------- * Enable processor retention * --------------------------- @@ -68,18 +95,14 @@ orr x0, x0, x1 msr L2ECTLR_EL1, x0 isb -#endif -#if ENABLE_CPU_DYNAMIC_RETENTION mrs x0, CPUECTLR_EL1 mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK orr x0, x0, x1 msr CPUECTLR_EL1, x0 isb -#endif -#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS /* ------------------------------------------------------- * Enable L2 and CPU ECTLR RW access from non-secure world * ------------------------------------------------------- @@ -88,13 +111,12 @@ msr actlr_el3, x0 msr actlr_el2, x0 isb -#endif /* -------------------------------- * Enable the cycle count register * -------------------------------- */ - mrs x0, pmcr_el0 +1: mrs x0, pmcr_el0 ubfx x0, x0, #11, #5 // read PMCR.N field mov x1, #1 lsl x0, x1, x0 diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index 750e6e3f..ca78d50e 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -48,20 +48,6 @@ #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN /******************************************************************************* - * Implementation defined ACTLR_EL3 bit definitions - ******************************************************************************/ -#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) -#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) -#define ACTLR_EL3_L2CTLR_BIT (1 << 4) -#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) -#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) -#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ - ACTLR_EL3_L2ECTLR_BIT | \ - ACTLR_EL3_L2CTLR_BIT | \ - ACTLR_EL3_CPUECTLR_BIT | \ - ACTLR_EL3_CPUACTLR_BIT) - -/******************************************************************************* * GIC memory map ******************************************************************************/ #define TEGRA_GICD_BASE 0x50041000 diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk index 36746e11..acc9384d 100644 --- a/plat/nvidia/tegra/soc/t210/platform_t210.mk +++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk @@ -37,15 +37,6 @@ $(eval $(call add_define,TZDRAM_BASE)) ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1 $(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT)) -ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1 -$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS)) - -ENABLE_L2_DYNAMIC_RETENTION := 1 -$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION)) - -ENABLE_CPU_DYNAMIC_RETENTION := 1 -$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION)) - PLATFORM_CLUSTER_COUNT := 2 $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) |