diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2016-02-03 09:51:25 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-03-20 09:14:05 -0700 |
| commit | 7dd5af0a09dc546e43f775b52150ded8383078c8 (patch) | |
| tree | e66e2dda5efaf6afbfea6c40f36f9ef6bed39acd | |
| parent | 7afd46375318bc912f6bb41362685371a003bb11 (diff) | |
Tegra186: add Video memory carveout settings
This patch supports the TEGRA_SIP_NEW_VIDEOMEM_REGION SiP call to
program new video memory carveout settings from the NS world.
Change-Id: If9ed818fe71e6cb7461f225090105a4d8883b7a2
Signed-off-by: Wayne Lin <wlin@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| -rw-r--r-- | plat/nvidia/tegra/soc/t186/plat_sip_calls.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c index 8c462f7f..66a433e9 100644 --- a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c @@ -36,6 +36,7 @@ #include <debug.h> #include <errno.h> #include <mce.h> +#include <memctrl.h> #include <runtime_svc.h> #include <t18x_ari.h> #include <tegra_private.h> @@ -106,6 +107,32 @@ int plat_sip_handler(uint32_t smc_fid, return 0; + case TEGRA_SIP_NEW_VIDEOMEM_REGION: + /* clean up the high bits */ + x1 = (uint32_t)x1; + x2 = (uint32_t)x2; + + /* + * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) + * or falls outside of the valid DRAM range + */ + mce_ret = bl31_check_ns_address(x1, x2); + if (mce_ret) + return -ENOTSUP; + + /* + * Check if Video Memory is aligned to 1MB. + */ + if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { + ERROR("Unaligned Video Memory base address!\n"); + return -ENOTSUP; + } + + /* new video memory carveout settings */ + tegra_memctrl_videomem_setup(x1, x2); + + return 0; + default: ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); break; |