diff options
| author | Qixiang Xu <qixiang.xu@arm.com> | 2017-08-31 11:45:32 +0800 |
|---|---|---|
| committer | David Cunado <david.cunado@arm.com> | 2017-09-12 15:21:13 +0100 |
| commit | fd5763ea8a8724593ae872d416abee850e93960d (patch) | |
| tree | becd9ad56cb522d5d7e5436fc6cdf60476fea69b | |
| parent | 50915b891e68e22557f5e3625d881e31fa29f2e2 (diff) | |
plat/arm: Fix BL31_BASE when RESET_TO_BL31=1
The value of BL31_BASE currently depends on the size of BL31. This
causes problems in the RESET_TO_BL31 case because the value of
BL31_BASE is used in the model launch parameters, which often changes.
Therefore, this patch fixes BL31_BASE to the middle of Trusted SRAM,
to avoid further model parameter changes in future.
Change-Id: I6d7fa4fe293717d84768974679539c0e0cb6d935
Signed-off-by: David Cunado <david.cunado@arm.com>
| -rw-r--r-- | docs/user-guide.rst | 36 | ||||
| -rw-r--r-- | include/plat/arm/common/arm_def.h | 7 |
2 files changed, 25 insertions, 18 deletions
diff --git a/docs/user-guide.rst b/docs/user-guide.rst index f66bde3e..1ff080d7 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -1593,15 +1593,15 @@ with 8 CPUs using the AArch64 build of ARM Trusted Firmware. -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ - -C cluster0.cpu0.RVBAR=0x04023000 \ - -C cluster0.cpu1.RVBAR=0x04023000 \ - -C cluster0.cpu2.RVBAR=0x04023000 \ - -C cluster0.cpu3.RVBAR=0x04023000 \ - -C cluster1.cpu0.RVBAR=0x04023000 \ - -C cluster1.cpu1.RVBAR=0x04023000 \ - -C cluster1.cpu2.RVBAR=0x04023000 \ - -C cluster1.cpu3.RVBAR=0x04023000 \ - --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000 \ + -C cluster0.cpu0.RVBAR=0x04020000 \ + -C cluster0.cpu1.RVBAR=0x04020000 \ + -C cluster0.cpu2.RVBAR=0x04020000 \ + -C cluster0.cpu3.RVBAR=0x04020000 \ + -C cluster1.cpu0.RVBAR=0x04020000 \ + -C cluster1.cpu1.RVBAR=0x04020000 \ + -C cluster1.cpu2.RVBAR=0x04020000 \ + -C cluster1.cpu3.RVBAR=0x04020000 \ + --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \ --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \ --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ @@ -1678,15 +1678,15 @@ boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware. -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cache_state_modelled=1 \ - -C cluster0.cpu0.RVBARADDR=0x04023000 \ - -C cluster0.cpu1.RVBARADDR=0x04023000 \ - -C cluster0.cpu2.RVBARADDR=0x04023000 \ - -C cluster0.cpu3.RVBARADDR=0x04023000 \ - -C cluster1.cpu0.RVBARADDR=0x04023000 \ - -C cluster1.cpu1.RVBARADDR=0x04023000 \ - -C cluster1.cpu2.RVBARADDR=0x04023000 \ - -C cluster1.cpu3.RVBARADDR=0x04023000 \ - --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000 \ + -C cluster0.cpu0.RVBARADDR=0x04020000 \ + -C cluster0.cpu1.RVBARADDR=0x04020000 \ + -C cluster0.cpu2.RVBARADDR=0x04020000 \ + -C cluster0.cpu3.RVBARADDR=0x04020000 \ + -C cluster1.cpu0.RVBARADDR=0x04020000 \ + -C cluster1.cpu1.RVBARADDR=0x04020000 \ + -C cluster1.cpu2.RVBARADDR=0x04020000 \ + -C cluster1.cpu3.RVBARADDR=0x04020000 \ + --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \ --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \ --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index efc276c6..787ccb02 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -292,6 +292,13 @@ #define BL31_BASE ARM_AP_TZC_DRAM1_BASE #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ PLAT_ARM_MAX_BL31_SIZE) +#elif (RESET_TO_BL31) +/* + * Put BL31_BASE in the middle of the Trusted SRAM. + */ +#define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \ + (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1)) +#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) #else /* * Put BL31 at the top of the Trusted SRAM. |