diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2016-03-28 15:05:03 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-03-23 14:19:34 -0700 |
| commit | 1b9ab0542e5b7ef1627e46fb6b57f183ff72c135 (patch) | |
| tree | e5c3bfe6bc9e809bbd38b34a988a1ed026c0d274 | |
| parent | c60f58ef0b1bc39a3b1fee691a28916d1e2b84a8 (diff) | |
Tegra186: program default core wake mask during CPU_SUSPEND
This patch programs the default CPU wake mask during CPU_SUSPEND. This
reduces the CPU_SUSPEND latency as the system has to send one less SMC
before issuing the actual suspend request.
Original change by Krishna Sitaraman <ksitaraman@nvidia.com>
Change-Id: I1f9351dde4ab30936070e9f42c2882fa691cbe46
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| -rw-r--r-- | plat/nvidia/tegra/soc/t186/plat_psci_handlers.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index 9b492fb8..536ecbf0 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -56,6 +56,8 @@ extern uint32_t __tegra186_cpu_reset_handler_data, /* constants to get power state's wake time */ #define TEGRA186_WAKE_TIME_MASK 0xFFFFFF #define TEGRA186_WAKE_TIME_SHIFT 4 +/* default core wake mask for CPU_SUSPEND */ +#define TEGRA186_CORE_WAKE_MASK 0x180c /* context size to save during system suspend */ #define TEGRA186_SE_CONTEXT_SIZE 3 @@ -124,12 +126,24 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) if (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) { + /* Program default wake mask */ + write_ctx_reg(gp_regs, CTX_GPREG_X4, 0); + write_ctx_reg(gp_regs, CTX_GPREG_X5, TEGRA186_CORE_WAKE_MASK); + write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); + (void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, 0, 0, 0); + /* Prepare for cpu idle */ (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C6, wake_time[cpu], 0); } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { + /* Program default wake mask */ + write_ctx_reg(gp_regs, CTX_GPREG_X4, 0); + write_ctx_reg(gp_regs, CTX_GPREG_X5, TEGRA186_CORE_WAKE_MASK); + write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); + (void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, 0, 0, 0); + /* Prepare for cpu powerdn */ (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, wake_time[cpu], 0); |