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| author | Soby Mathew <soby.mathew@arm.com> | 2019-05-28 13:18:41 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-05-28 13:18:41 +0000 |
| commit | 68b8ab0bbcfbce893731b3db85cebe7cad73e37a (patch) | |
| tree | 1006e6c8f0459a78c96f3d21f106eb409fc9ee38 | |
| parent | 89a4d269146c90e944ea36d4afb39b27d82b23e2 (diff) | |
| parent | 16a755f375db581b6381f62cc0dd90963a4f61cb (diff) | |
Merge changes from topic "for-upstream" into integration
* changes:
ti: k3: common: Set L2 latency on A72 cores
ti: k3: common: Add support for J721E
| -rw-r--r-- | plat/ti/k3/common/k3_helpers.S | 22 | ||||
| -rw-r--r-- | plat/ti/k3/common/plat_common.mk | 4 |
2 files changed, 26 insertions, 0 deletions
diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S index 1ab1af54..3afca591 100644 --- a/plat/ti/k3/common/k3_helpers.S +++ b/plat/ti/k3/common/k3_helpers.S @@ -6,6 +6,8 @@ #include <arch.h> #include <asm_macros.S> +#include <cortex_a72.h> +#include <cpu_macros.S> #include <platform_def.h> #define K3_BOOT_REASON_COLD_RESET 0x1 @@ -89,6 +91,26 @@ out: ret endfunc plat_my_core_pos + /* -------------------------------------------------------------------- + * This handler does the following: + * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72 + * -------------------------------------------------------------------- + */ + .globl plat_reset_handler +func plat_reset_handler + /* Only on Cortex-A72 */ + jump_if_cpu_midr CORTEX_A72_MIDR, a72 + ret + + /* Cortex-A72 specific settings */ +a72: + mrs x0, CORTEX_A72_L2CTLR_EL1 + orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) + msr CORTEX_A72_L2CTLR_EL1, x0 + isb + ret +endfunc plat_reset_handler + /* --------------------------------------------- * int plat_crash_console_init(void) * Function to initialize the crash console diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk index 29fcafdb..2e5f5845 100644 --- a/plat/ti/k3/common/plat_common.mk +++ b/plat/ti/k3/common/plat_common.mk @@ -22,6 +22,9 @@ ERRATA_A53_836870 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 +# A72 Erratum for SoC +ERRATA_A72_859971 := 1 + # Split out RO data into a non-executable section SEPARATE_CODE_AND_RODATA := 1 @@ -68,6 +71,7 @@ K3_TI_SCI_SOURCES += \ PLAT_BL_COMMON_SOURCES += \ lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a72.S \ ${XLAT_TABLES_LIB_SRCS} \ ${K3_CONSOLE_SOURCES} \ |