diff options
| author | Konstantin Porotchkin <kostap@marvell.com> | 2018-07-05 11:28:02 +0300 |
|---|---|---|
| committer | Konstantin Porotchkin <kostap@marvell.com> | 2018-07-18 18:48:30 +0300 |
| commit | bc6206f7f62ec8e466bbab82dd576bc8489486e2 (patch) | |
| tree | 52dc5c19e397b7dcb4b94874c9e279d00b084585 | |
| parent | 031542fc24ba48c2f38cb40ab008afb9943aaa74 (diff) | |
lib: cpu: Add L2 cache aux control register definition to CA72
Add definition of EL1 L2 Auxilary Control register to
Cortex A72 library headers.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a72.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 9f184706..f5ca2ee7 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -38,6 +38,13 @@ #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) /******************************************************************************* + * L2 Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0 + +#define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14) + +/******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 |