diff options
| author | Eleanor Bonnici <Eleanor.bonnici@arm.com> | 2017-08-10 14:46:26 +0100 |
|---|---|---|
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-08-29 13:52:48 +0100 |
| commit | d0e1094ea0610eb825b93e20145bebde657745f0 (patch) | |
| tree | e8db5fd62b87c46482fee1ea9516aa6d074f8ef8 | |
| parent | f9a856ba9f558ec107f2793d68e93a75e4eddc22 (diff) | |
Tegra: Rename CORTEX_A57_ACTLR_EL1 to *CPUACTLR*
CORTEX_A57_ACTLR_EL1 macro refers to the CPUACTLR_EL1 register. Since
ACTLR_EL1 is a different register (not implemented in Cortex-A57) this
patch renames this macro for clarity.
Change-Id: I94d7d564cd2423ae032bbdd59a99d2dc535cdff6
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
| -rw-r--r-- | plat/nvidia/tegra/common/aarch64/tegra_helpers.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index 691b90af..3c490d07 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -316,18 +316,18 @@ func tegra_secure_entrypoint _align=6 * entries from the branch predictor array. * ------------------------------------------------------- */ - mrs x0, CORTEX_A57_ACTLR_EL1 + mrs x0, CORTEX_A57_CPUACTLR_EL1 orr x0, x0, #1 - msr CORTEX_A57_ACTLR_EL1, x0 /* invalidate BTB and I$ together */ + msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ dsb sy isb ic iallu /* actual invalidate */ dsb sy isb - mrs x0, CORTEX_A57_ACTLR_EL1 + mrs x0, CORTEX_A57_CPUACTLR_EL1 bic x0, x0, #1 - msr CORTEX_A57_ACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ + msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ dsb sy isb @@ -351,7 +351,7 @@ func tegra_secure_entrypoint _align=6 msr oslar_el1, x0 /* os lock stays 0 across warm reset */ mov x3, #3 movz x4, #0x8000, lsl #48 - msr CORTEX_A57_ACTLR_EL1, x4 /* turn off RCG */ + msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */ isb msr rmr_el3, x3 /* request warm reset */ isb |