diff options
author | Chris Kay <chris.kay@arm.com> | 2018-05-10 14:27:45 +0100 |
---|---|---|
committer | Chris Kay <chris.kay@arm.com> | 2018-05-11 15:37:47 +0100 |
commit | d7ecac73b58e3350e0e89b0e8d03f445ed78aa47 (patch) | |
tree | f3ce1bbc44d8b6c48527730c8a8273c6d783fa88 | |
parent | 885ca54a75e14a63c375b5d12852dc7ef2c0b568 (diff) |
css: Fix erroneous non-secure RAM base address/size for SGI-575
SGI-575's NSRAM is neither in the same place nor the same size as Juno's.
Change-Id: Id6d692e9c7e9c1360014bb525eda966ebe29c823
Signed-off-by: Chris Kay <chris.kay@arm.com>
-rw-r--r-- | include/plat/arm/css/common/css_def.h | 3 | ||||
-rw-r--r-- | plat/arm/board/juno/include/platform_def.h | 3 | ||||
-rw-r--r-- | plat/arm/css/sgi/include/platform_def.h | 3 |
3 files changed, 6 insertions, 3 deletions
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index deea1bb4..275e591a 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -22,9 +22,6 @@ #define CSS_DEVICE_BASE 0x20000000 #define CSS_DEVICE_SIZE 0x0e000000 -#define NSRAM_BASE 0x2e000000 -#define NSRAM_SIZE 0x00008000 - /* System Security Control Registers */ #define SSC_REG_BASE 0x2a420000 #define SSC_GPRETN (SSC_REG_BASE + 0x030) diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index c8349413..e616e1fc 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -56,6 +56,9 @@ /* Use the bypass address */ #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET +#define NSRAM_BASE 0x2e000000 +#define NSRAM_SIZE 0x00008000 /* 32KB */ + /* virtual address used by dynamic mem_protect for chunk_base */ #define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000 diff --git a/plat/arm/css/sgi/include/platform_def.h b/plat/arm/css/sgi/include/platform_def.h index 62f40599..49a33ad6 100644 --- a/plat/arm/css/sgi/include/platform_def.h +++ b/plat/arm/css/sgi/include/platform_def.h @@ -52,6 +52,9 @@ #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ +#define PLAT_ARM_NSRAM_BASE 0x06000000 +#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ + #define PLAT_MAX_PWR_LVL 1 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ |