diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2016-12-12 14:24:17 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-04-05 14:09:51 -0700 |
| commit | dec349c87d99ec91ef3b00aa14a937a1fe237703 (patch) | |
| tree | 7aaa82112d070d735a27ca77956983299994b7a9 | |
| parent | d81938ab3a56d5e75ab9c43f9f496f438700854f (diff) | |
Tegra186: move platform specific MCE defines to tegra_def.h
This patch moves the MCE's configurable parameters to tegra_def.h for
the Tegra186 SoC, to allow forward compatiblity.
Change-Id: If8660c1c09908a4064dbb67d5ca4fb78389cab13
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| -rw-r--r-- | plat/nvidia/tegra/include/t186/tegra_def.h | 30 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t186/drivers/include/mce.h | 40 |
2 files changed, 30 insertions, 40 deletions
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index a394a723..b5a8ab38 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -32,6 +32,36 @@ #define __TEGRA_DEF_H__ /******************************************************************************* + * MCE apertures used by the ARI interface + * + * Aperture 0 - Cpu0 (ARM Cortex A-57) + * Aperture 1 - Cpu1 (ARM Cortex A-57) + * Aperture 2 - Cpu2 (ARM Cortex A-57) + * Aperture 3 - Cpu3 (ARM Cortex A-57) + * Aperture 4 - Cpu4 (Denver15) + * Aperture 5 - Cpu5 (Denver15) + ******************************************************************************/ +#define MCE_ARI_APERTURE_0_OFFSET 0x0 +#define MCE_ARI_APERTURE_1_OFFSET 0x10000 +#define MCE_ARI_APERTURE_2_OFFSET 0x20000 +#define MCE_ARI_APERTURE_3_OFFSET 0x30000 +#define MCE_ARI_APERTURE_4_OFFSET 0x40000 +#define MCE_ARI_APERTURE_5_OFFSET 0x50000 +#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET + +/* number of apertures */ +#define MCE_ARI_APERTURES_MAX 6 + +/* each ARI aperture is 64KB */ +#define MCE_ARI_APERTURE_SIZE 0x10000 + +/******************************************************************************* + * CPU core id macros for the MCE_ONLINE_CORE ARI + ******************************************************************************/ +#define MCE_CORE_ID_MAX 8 +#define MCE_CORE_ID_MASK 0x7 + +/******************************************************************************* * These values are used by the PSCI implementation during the `CPU_SUSPEND` * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' * parameter. diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h index 61ca5ebe..441a2c1b 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h @@ -35,46 +35,6 @@ #include <tegra_def.h> /******************************************************************************* - * MCE apertures used by the ARI interface - * - * Aperture 0 - Cpu0 (ARM Cortex A-57) - * Aperture 1 - Cpu1 (ARM Cortex A-57) - * Aperture 2 - Cpu2 (ARM Cortex A-57) - * Aperture 3 - Cpu3 (ARM Cortex A-57) - * Aperture 4 - Cpu4 (Denver15) - * Aperture 5 - Cpu5 (Denver15) - ******************************************************************************/ -#define MCE_ARI_APERTURE_0_OFFSET 0x0 -#define MCE_ARI_APERTURE_1_OFFSET 0x10000 -#define MCE_ARI_APERTURE_2_OFFSET 0x20000 -#define MCE_ARI_APERTURE_3_OFFSET 0x30000 -#define MCE_ARI_APERTURE_4_OFFSET 0x40000 -#define MCE_ARI_APERTURE_5_OFFSET 0x50000 -#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET - -/* number of apertures */ -#define MCE_ARI_APERTURES_MAX 6 - -/* each ARI aperture is 64KB */ -#define MCE_ARI_APERTURE_SIZE 0x10000 - -/******************************************************************************* - * CPU core ids - used by the MCE_ONLINE_CORE ARI - ******************************************************************************/ -typedef enum mce_core_id { - MCE_CORE_ID_DENVER_15_0, - MCE_CORE_ID_DENVER_15_1, - /* 2 and 3 are reserved */ - MCE_CORE_ID_A57_0 = 4, - MCE_CORE_ID_A57_1, - MCE_CORE_ID_A57_2, - MCE_CORE_ID_A57_3, - MCE_CORE_ID_MAX -} mce_core_id_t; - -#define MCE_CORE_ID_MASK 0x7 - -/******************************************************************************* * MCE commands ******************************************************************************/ typedef enum mce_cmd { |