diff options
author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2013-11-27 09:38:52 +0000 |
---|---|---|
committer | Dan Handley <dan.handley@arm.com> | 2013-12-05 11:33:15 +0000 |
commit | 8d69a03f6a7db3c437b7cfdd15402627277d8cb4 (patch) | |
tree | a74ad7b72757ed85d084bf50ce20feb4164c2eb6 /bl1/bl1.ld.S | |
parent | 3e850a84c94a5f1bc0141041ad32be94460716f7 (diff) |
Various improvements/cleanups on the linker scripts
- Check at link-time that bootloader images will fit in memory
at run time and that they won't overlap each other.
- Remove text and rodata orphan sections.
- Define new linker symbols to remove the need for platform setup
code to know the order of sections.
- Reduce the size of the raw binary images by cutting some sections
out of the disk image and allocating them at load time, whenever
possible.
- Rework alignment constraints on sections.
- Remove unused linker symbols.
- Homogenize linker symbols names across all BLs.
- Add some comments in the linker scripts.
Change-Id: I47a328af0ccc7c8ab47fcc0dc6e7dd26160610b9
Diffstat (limited to 'bl1/bl1.ld.S')
-rw-r--r-- | bl1/bl1.ld.S | 86 |
1 files changed, 53 insertions, 33 deletions
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index 53277155..b3f169f7 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -34,57 +34,77 @@ OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) MEMORY { - /* ROM is read-only and executable */ ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE - /* RAM is read/write and Initialised */ RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE } SECTIONS { - FIRMWARE_ROM : { - *(reset_code) + ro : { + __RO_START__ = .; + *bl1_entrypoint.o(.text) *(.text) - *(.rodata) + *(.rodata*) + __RO_END__ = .; } >ROM - .bss : { - __BSS_RAM_START__ = .; - *(.bss) - *(COMMON) - __BSS_RAM_STOP__ = .; - } >RAM AT>ROM - - .data : { + /* + * The .data section gets copied from ROM to RAM at runtime. + * Its LMA and VMA must be 16-byte aligned. + */ + . = NEXT(16); /* Align LMA */ + .data : ALIGN(16) { /* Align VMA */ __DATA_RAM_START__ = .; *(.data) - __DATA_RAM_STOP__ = .; - } >RAM AT>ROM + __DATA_RAM_END__ = .; + } >RAM AT>ROM - FIRMWARE_RAM_STACKS ALIGN (PLATFORM_CACHE_LINE_SIZE) : { - . += 0x1000; + stacks (NOLOAD) : { + __STACKS_START__ = .; *(tzfw_normal_stacks) - . = ALIGN(4096); - } >RAM AT>ROM + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(.bss) + *(COMMON) + __BSS_END__ = .; + } >RAM - FIRMWARE_RAM_COHERENT ALIGN (4096): { + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; *(tzfw_coherent_mem) -/* . += 0x1000;*/ -/* Do we need to make sure this is at least 4k? */ - . = ALIGN(4096); + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; } >RAM - __FIRMWARE_ROM_START__ = LOADADDR(FIRMWARE_ROM); - __FIRMWARE_ROM_SIZE__ = SIZEOF(FIRMWARE_ROM); + __BL1_RAM_START__ = ADDR(.data); + __BL1_RAM_END__ = .; + + __DATA_ROM_START__ = LOADADDR(.data); + __DATA_SIZE__ = SIZEOF(.data); - __FIRMWARE_DATA_START__ = LOADADDR(.data); - __FIRMWARE_DATA_SIZE__ = SIZEOF(.data); + __BSS_SIZE__ = SIZEOF(.bss); - __FIRMWARE_BSS_START__ = LOADADDR(.bss); - __FIRMWARE_BSS_SIZE__ = SIZEOF(.bss); + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; - __FIRMWARE_RAM_STACKS_START__ = LOADADDR(FIRMWARE_RAM_STACKS); - __FIRMWARE_RAM_STACKS_SIZE__ = SIZEOF(FIRMWARE_RAM_STACKS); - __FIRMWARE_RAM_COHERENT_START__ = LOADADDR(FIRMWARE_RAM_COHERENT); - __FIRMWARE_RAM_COHERENT_SIZE__ = SIZEOF(FIRMWARE_RAM_COHERENT); + ASSERT(. <= BL31_BASE, "BL31 image overlaps BL1 image.") } |