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| author | Andrew Thoelke <andrew.thoelke@arm.com> | 2015-06-11 14:12:14 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2015-06-19 11:29:41 +0100 |
| commit | 354ab57dba7f81bfa2f2878a3864c39e1839bd06 (patch) | |
| tree | 43971ef60b83b7894fe8a20ae8d21af2b04a57b1 /bl1/bl1_main.c | |
| parent | 79b1ebdaae021c0a9c4880849d181a5b91ecac8a (diff) | |
Fix incorrect assertions in bl1_main()
The validation of the caching enable state in bl1_main() was
incorrect resulting in the state not being checked. Using the right
operator fixes this.
Change-Id: I2a99478f420281a1dcdf365d3d4fd8394cd21b51
Diffstat (limited to 'bl1/bl1_main.c')
| -rw-r--r-- | bl1/bl1_main.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index a5db0855..a7a872ce 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -126,9 +126,9 @@ void bl1_main(void) * Ensure that MMU/Caches and coherency are turned on */ val = read_sctlr_el3(); - assert(val | SCTLR_M_BIT); - assert(val | SCTLR_C_BIT); - assert(val | SCTLR_I_BIT); + assert(val & SCTLR_M_BIT); + assert(val & SCTLR_C_BIT); + assert(val & SCTLR_I_BIT); /* * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the * provided platform value |