diff options
| author | Dan Handley <dan.handley@arm.com> | 2015-03-30 17:15:16 +0100 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2015-04-27 18:05:06 +0100 |
| commit | ce4c820d8ccf803dac0329cabdd6e75c78e81f4e (patch) | |
| tree | 65ec4e21ba293bc53bc58c182805e05e0873918f /bl1 | |
| parent | 1b70db06ff8dcd34c4d6ad5a3499f602318d376d (diff) | |
Remove use of PLATFORM_CACHE_LINE_SIZE
The required platform constant PLATFORM_CACHE_LINE_SIZE is
unnecessary since CACHE_WRITEBACK_GRANULE effectively provides the
same information. CACHE_WRITEBACK_GRANULE is preferred since this
is an architecturally defined term and allows comparison with the
corresponding hardware register value.
Replace all usage of PLATFORM_CACHE_LINE_SIZE with
CACHE_WRITEBACK_GRANULE.
Also, add a runtime assert in BL1 to check that the provided
CACHE_WRITEBACK_GRANULE matches the value provided in CTR_EL0.
Change-Id: If87286be78068424217b9f3689be358356500dcd
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/bl1_main.c | 29 |
1 files changed, 22 insertions, 7 deletions
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index 491fd5cf..a5db0855 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -114,21 +114,36 @@ void bl1_main(void) INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT); -#if DEBUG - unsigned long sctlr_el3 = read_sctlr_el3(); -#endif image_info_t bl2_image_info = { {0} }; entry_point_info_t bl2_ep = { {0} }; meminfo_t *bl1_tzram_layout; meminfo_t *bl2_tzram_layout = 0x0; int err; +#if DEBUG + unsigned long val; /* * Ensure that MMU/Caches and coherency are turned on */ - assert(sctlr_el3 | SCTLR_M_BIT); - assert(sctlr_el3 | SCTLR_C_BIT); - assert(sctlr_el3 | SCTLR_I_BIT); + val = read_sctlr_el3(); + assert(val | SCTLR_M_BIT); + assert(val | SCTLR_C_BIT); + assert(val | SCTLR_I_BIT); + /* + * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the + * provided platform value + */ + val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; + /* + * If CWG is zero, then no CWG information is available but we can + * at least check the platform value is less than the architectural + * maximum. + */ + if (val != 0) + assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); + else + assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); +#endif /* Perform remaining generic architectural setup from EL3 */ bl1_arch_setup(); |