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| author | Andrew F. Davis <afd@ti.com> | 2019-05-10 11:20:50 -0400 |
|---|---|---|
| committer | Andrew F. Davis <afd@ti.com> | 2019-05-22 12:07:52 -0500 |
| commit | 16a755f375db581b6381f62cc0dd90963a4f61cb (patch) | |
| tree | bfa535bf7620ba4d3a1a6f901de44e7a975271d2 /docs/components/exception-handling.rst | |
| parent | 7c088e710b1c342715ec9b000d07ed6964becac6 (diff) | |
ti: k3: common: Set L2 latency on A72 cores
The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a
Diffstat (limited to 'docs/components/exception-handling.rst')
0 files changed, 0 insertions, 0 deletions