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| author | Bai Ping <ping.bai@nxp.com> | 2018-08-20 17:32:21 +0800 |
|---|---|---|
| committer | Bai Ping <ping.bai@nxp.com> | 2018-08-20 17:40:45 +0800 |
| commit | 079eebba34b09d6f9ffeb70d999fb4a065008b1c (patch) | |
| tree | 464b39f3dee8f152c685bc4eae7b479a2179b8ec /docs/diagrams/rt-svc-descs-layout.png | |
| parent | 11248af8bd01fe232c4f3c8f510d157b1d210dca (diff) | |
MLK-19256 plat: imx8mm: correct dram apb clock rate dvfs
The DRAM APB bus clock rate is wrong before and after DVFS.
The register offset for APB bus clock is wrong, so fix it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'docs/diagrams/rt-svc-descs-layout.png')
0 files changed, 0 insertions, 0 deletions