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| author | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-21 17:35:07 +0000 |
|---|---|---|
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-26 16:21:06 +0000 |
| commit | 508d71108a06c7fce2eeef78659b9b7739cee6eb (patch) | |
| tree | 0a79684da2ea12a62188da7d4415598f2a0d4398 /docs/platform-interrupt-controller-API.rst | |
| parent | 98551591f5371de2c2f0dee6be2e12b75653f04d (diff) | |
Add workaround for errata 1130799 for Cortex-A76
TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.
Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'docs/platform-interrupt-controller-API.rst')
0 files changed, 0 insertions, 0 deletions