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| author | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-25 15:17:44 +0000 |
|---|---|---|
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-26 16:21:06 +0000 |
| commit | 5c6aa01affe14c40efdebdc9450cdbc4ae0bc494 (patch) | |
| tree | 4642c4f18dec3b95d02884414f2bc5124c756dc8 /docs/platform-interrupt-controller-API.rst | |
| parent | 5cc8c7ba1b24ace2ef7345e96d933141f3609817 (diff) | |
Add workaround for errata 1073348 for Cortex-A76
Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.
Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'docs/platform-interrupt-controller-API.rst')
0 files changed, 0 insertions, 0 deletions