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| author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2019-02-18 16:55:43 +0000 |
|---|---|---|
| committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2019-02-18 17:03:16 +0000 |
| commit | ed4fc6f026999daad19b4bb47e6b6626078206c2 (patch) | |
| tree | 66a71202b0a92fae01a1e2b10c69235a5f358a72 /docs/platform-interrupt-controller-API.rst | |
| parent | fa233ac9d435905d2717a9880cfb3a1671e37134 (diff) | |
Disable processor Cycle Counting in Secure state
In a system with ARMv8.5-PMU implemented:
- If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting
in Secure state in PMCCNTR.
- If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in
Secure state in PMCCNTR_EL0.
So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64)
or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure
as any EL can change that value.
Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'docs/platform-interrupt-controller-API.rst')
0 files changed, 0 insertions, 0 deletions