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| author | Joel Hutton <Joel.Hutton@Arm.com> | 2019-04-09 14:45:34 +0100 |
|---|---|---|
| committer | Joel Hutton <Joel.Hutton@arm.com> | 2019-04-10 10:57:58 +0100 |
| commit | f999faca06e8ff5d6d23a08d844c6a4ad38e3000 (patch) | |
| tree | 0a4bdd798e26ca9e54018ce623252bb611ce6536 /docs/platform-interrupt-controller-API.rst | |
| parent | a738e1554c2daf7511af3543addd07c956268d14 (diff) | |
Add note about erratum 814220 for A7
On Cortex-A7 an L2 set/way cache maintenance operation can overtake
an L1 set/way cache maintenance operation. The mitigation for this is
to use a `DSB` instruction before changing cache. The cache cleaning
code happens to already be doing this, so only a comment was added.
Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Diffstat (limited to 'docs/platform-interrupt-controller-API.rst')
0 files changed, 0 insertions, 0 deletions