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| author | danh-arm <dan.handley@arm.com> | 2015-06-24 11:23:33 +0100 |
|---|---|---|
| committer | danh-arm <dan.handley@arm.com> | 2015-06-24 11:23:33 +0100 |
| commit | e347e843a93b84b64de935b61e64b4f31d54eef3 (patch) | |
| tree | 0094b9566fa606ab0c456c6dfbe146d98307c9bd /docs/porting-guide.md | |
| parent | f1f99f3af580ddb8a703cc5efb424c74c8cb5a92 (diff) | |
| parent | bf031bba2b9dfc994a7d0c18dfc5e64469cee480 (diff) | |
Merge pull request #310 from sandrine-bailleux/sb/tf-issue-304-phase1
Enhance BL3-1 entrypoint handling to support non-TF boot firmware - Phase 1
Diffstat (limited to 'docs/porting-guide.md')
| -rw-r--r-- | docs/porting-guide.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/porting-guide.md b/docs/porting-guide.md index 1e49deb8..436dc106 100644 --- a/docs/porting-guide.md +++ b/docs/porting-guide.md @@ -434,7 +434,7 @@ This function fulfills requirement 1 and 3 listed above. This function is called with the MMU and data caches disabled. It is responsible for placing the executing secondary CPU in a platform-specific state until the primary CPU performs the necessary actions to bring it out of that state and -allow entry into the OS. +allow entry into the OS. This function must not return. In the ARM FVP port, each secondary CPU powers itself off. The primary CPU is responsible for powering up the secondary CPU when normal world software @@ -569,7 +569,7 @@ preserve the values of callee saved registers x19 to x29. The default implementation doesn't do anything. If a platform needs to override the default implementation, refer to the [Firmware Design] for general -guidelines regarding placement of code in a reset handler. +guidelines. ### Function : plat_disable_acp() |