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| author | Soby Mathew <soby.mathew@arm.com> | 2019-05-03 13:35:38 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-05-03 13:35:38 +0000 |
| commit | 854ca7daf9bbf4762d698128bfe030e0cebea956 (patch) | |
| tree | 88258bb259ac6847ea95944add2f4c9ac0c832df /docs/user-guide.rst | |
| parent | b9c1d185bbd8778835017560da916daa39709e78 (diff) | |
| parent | 076b5f02e2747ef1b5a55f1c5d368df16f046b1c (diff) | |
Merge "Add compile-time errors for HW_ASSISTED_COHERENCY flag" into integration
Diffstat (limited to 'docs/user-guide.rst')
| -rw-r--r-- | docs/user-guide.rst | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 2a21bd21..4068c9a3 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -534,13 +534,21 @@ Common build options - ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific software operations are required for CPUs to enter and exit coherency. - However, there exists newer systems where CPUs' entry to and exit from - coherency is managed in hardware. Such systems require software to only - initiate the operations, and the rest is managed in hardware, minimizing - active software management. In such systems, this boolean option enables - TF-A to carry out build and run-time optimizations during boot and power - management operations. This option defaults to 0 and if it is enabled, - then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. + However, newer systems exist where CPUs' entry to and exit from coherency + is managed in hardware. Such systems require software to only initiate these + operations, and the rest is managed in hardware, minimizing active software + management. In such systems, this boolean option enables TF-A to carry out + build and run-time optimizations during boot and power management operations. + This option defaults to 0 and if it is enabled, then it implies + ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. + + If this flag is disabled while the platform which TF-A is compiled for + includes cores that manage coherency in hardware, then a compilation error is + generated. This is based on the fact that a system cannot have, at the same + time, cores that manage coherency in hardware and cores that don't. In other + words, a platform cannot have, at the same time, cores that require + ``HW_ASSISTED_COHERENCY=1`` and cores that require + ``HW_ASSISTED_COHERENCY=0``. Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of translation library (xlat tables v2) must be used; version 1 of translation |