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| author | Caesar Wang <wxt@rock-chips.com> | 2016-10-27 01:13:16 +0800 |
|---|---|---|
| committer | Caesar Wang <wxt@rock-chips.com> | 2016-10-27 07:14:26 +0800 |
| commit | 2831bc3a5f5dd9cdd6f272044f9f916e68797ff1 (patch) | |
| tree | 08bf56a2c207d00dccb33ebf78ce92c1016d874a /drivers/arm/ccn/ccn.c | |
| parent | f9ba21bee5f660817d20ddcb094cdb9aabf0df7d (diff) | |
rockchip: add support save/restore configuration for DDR during enter S3
This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.
Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Diffstat (limited to 'drivers/arm/ccn/ccn.c')
0 files changed, 0 insertions, 0 deletions