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author | davidcunado-arm <david.cunado@arm.com> | 2017-04-21 17:10:27 +0100 |
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committer | GitHub <noreply@github.com> | 2017-04-21 17:10:27 +0100 |
commit | 484acce376e63b228befb06f3d10d0caf7067091 (patch) | |
tree | 5c8a4105ae878e70d19211ed99a6a53a0394ce5d /include/common/aarch32 | |
parent | 94e0ed6052352c1f0b90d43253f78fc98b1b7f12 (diff) | |
parent | 6f249345e2aa2343ce67222e82dafc539e973ec5 (diff) |
Merge pull request #910 from dp-arm/dp/AArch32-juno-port
Add AArch32 support for Juno
Diffstat (limited to 'include/common/aarch32')
-rw-r--r-- | include/common/aarch32/asm_macros.S | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/include/common/aarch32/asm_macros.S b/include/common/aarch32/asm_macros.S index 45023a0b..7b141da6 100644 --- a/include/common/aarch32/asm_macros.S +++ b/include/common/aarch32/asm_macros.S @@ -134,4 +134,37 @@ .space SPINLOCK_ASM_SIZE .endm + /* + * Helper macro to OR the bottom 32 bits of `_val` into `_reg_l` + * and the top 32 bits of `_val` into `_reg_h`. If either the bottom + * or top word of `_val` is zero, the corresponding OR operation + * is skipped. + */ + .macro orr64_imm _reg_l, _reg_h, _val + .if (\_val >> 32) + orr \_reg_h, \_reg_h, #(\_val >> 32) + .endif + .if (\_val & 0xffffffff) + orr \_reg_l, \_reg_l, #(\_val & 0xffffffff) + .endif + .endm + + /* + * Helper macro to bitwise-clear bits in `_reg_l` and + * `_reg_h` given a 64 bit immediate `_val`. The set bits + * in the bottom word of `_val` dictate which bits from + * `_reg_l` should be cleared. Similarly, the set bits in + * the top word of `_val` dictate which bits from `_reg_h` + * should be cleared. If either the bottom or top word of + * `_val` is zero, the corresponding BIC operation is skipped. + */ + .macro bic64_imm _reg_l, _reg_h, _val + .if (\_val >> 32) + bic \_reg_h, \_reg_h, #(\_val >> 32) + .endif + .if (\_val & 0xffffffff) + bic \_reg_l, \_reg_l, #(\_val & 0xffffffff) + .endif + .endm + #endif /* __ASM_MACROS_S__ */ |