diff options
| author | Yatharth Kochar <yatharth.kochar@arm.com> | 2016-11-10 16:17:51 +0000 |
|---|---|---|
| committer | dp-arm <dimitris.papastamos@arm.com> | 2017-04-20 15:05:21 +0100 |
| commit | dc787588a557d09fbf46c8562d7060cd39e275d9 (patch) | |
| tree | 537dc2995f41ad2e81fb9b2362c051c58ce09dfa /include/common/aarch32 | |
| parent | 0498343ac0d0b03c0389ce358bcb2f17096949dd (diff) | |
AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor
This patch adds AArch32 state support for ARM Cortex-A53,
Cortex-A57 and Cortex-A72 MPCore Processor in the CPU specific
operations framework.
NOTE: CPU errata handling code is not present in this patch.
Change-Id: I01eb3e028e40dde37565707ebc99e06e7a0c113d
Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com>
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
Diffstat (limited to 'include/common/aarch32')
| -rw-r--r-- | include/common/aarch32/asm_macros.S | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/include/common/aarch32/asm_macros.S b/include/common/aarch32/asm_macros.S index 45023a0b..7b141da6 100644 --- a/include/common/aarch32/asm_macros.S +++ b/include/common/aarch32/asm_macros.S @@ -134,4 +134,37 @@ .space SPINLOCK_ASM_SIZE .endm + /* + * Helper macro to OR the bottom 32 bits of `_val` into `_reg_l` + * and the top 32 bits of `_val` into `_reg_h`. If either the bottom + * or top word of `_val` is zero, the corresponding OR operation + * is skipped. + */ + .macro orr64_imm _reg_l, _reg_h, _val + .if (\_val >> 32) + orr \_reg_h, \_reg_h, #(\_val >> 32) + .endif + .if (\_val & 0xffffffff) + orr \_reg_l, \_reg_l, #(\_val & 0xffffffff) + .endif + .endm + + /* + * Helper macro to bitwise-clear bits in `_reg_l` and + * `_reg_h` given a 64 bit immediate `_val`. The set bits + * in the bottom word of `_val` dictate which bits from + * `_reg_l` should be cleared. Similarly, the set bits in + * the top word of `_val` dictate which bits from `_reg_h` + * should be cleared. If either the bottom or top word of + * `_val` is zero, the corresponding BIC operation is skipped. + */ + .macro bic64_imm _reg_l, _reg_h, _val + .if (\_val >> 32) + bic \_reg_h, \_reg_h, #(\_val >> 32) + .endif + .if (\_val & 0xffffffff) + bic \_reg_l, \_reg_l, #(\_val & 0xffffffff) + .endif + .endm + #endif /* __ASM_MACROS_S__ */ |