diff options
| author | David Cunado <david.cunado@arm.com> | 2016-10-31 17:37:34 +0000 |
|---|---|---|
| committer | David Cunado <david.cunado@arm.com> | 2016-11-09 15:45:06 +0000 |
| commit | 495f3d3c51096de3559cc7fb77494a16fc158e26 (patch) | |
| tree | 0f63e1ee431d91bfa7c5bacbe2e0c7630f7cc119 /include/common | |
| parent | 90d2956aeaa9f0838400eb40d6c48935ec4c988b (diff) | |
Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR
In order to avoid unexpected traps into EL3/MON mode, this patch
resets the debug registers, MDCR_EL3 and MDCR_EL2 for AArch64,
and SDCR and HDCR for AArch32.
MDCR_EL3/SDCR is zero'ed when EL3/MON mode is entered, at the
start of BL1 and BL31/SMP_MIN.
For MDCR_EL2/HDCR, this patch zero's the bits that are
architecturally UNKNOWN values on reset. This is done when
exiting from EL3/MON mode but only on platforms that support
EL2/HYP mode but choose to exit to EL1/SVC mode.
Fixes ARM-software/tf-issues#430
Change-Id: Idb992232163c072faa08892251b5626ae4c3a5b6
Signed-off-by: David Cunado <david.cunado@arm.com>
Diffstat (limited to 'include/common')
| -rw-r--r-- | include/common/aarch32/el3_common_macros.S | 8 | ||||
| -rw-r--r-- | include/common/aarch64/el3_common_macros.S | 7 |
2 files changed, 15 insertions, 0 deletions
diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S index 50ce952f..0018ea4b 100644 --- a/include/common/aarch32/el3_common_macros.S +++ b/include/common/aarch32/el3_common_macros.S @@ -67,6 +67,14 @@ orr r0, r0, #SCR_SIF_BIT stcopr r0, SCR + /* ----------------------------------------------------------------- + * Reset those registers that may have architecturally unknown reset + * values + * ----------------------------------------------------------------- + */ + mov r0, #0 + stcopr r0, SDCR + /* ----------------------------------------------------- * Enable the Asynchronous data abort now that the * exception vectors have been setup. diff --git a/include/common/aarch64/el3_common_macros.S b/include/common/aarch64/el3_common_macros.S index 9b22a734..a4189116 100644 --- a/include/common/aarch64/el3_common_macros.S +++ b/include/common/aarch64/el3_common_macros.S @@ -77,6 +77,13 @@ */ mov x0, #(SCR_RES1_BITS | SCR_EA_BIT | SCR_SIF_BIT) msr scr_el3, x0 + + /* --------------------------------------------------------------------- + * Reset registers that may have architecturally unknown reset values + * --------------------------------------------------------------------- + */ + msr mdcr_el3, xzr + /* --------------------------------------------------------------------- * Enable External Aborts and SError Interrupts now that the exception * vectors have been setup. |