diff options
author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-09-22 08:32:09 +0100 |
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committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-10-16 16:50:01 +0100 |
commit | fa9db4230aef4411cc6c56557f0c407326421876 (patch) | |
tree | 6ae9acc76ecca1db193c939e2b0d4ee538f2f52d /include/drivers/arm | |
parent | eb68ea9b10c190c237216dee92166f9e7b2ce3d4 (diff) |
GICv2: Add driver API to set PE target mask
The PE target mask is used to translate linear PE index (returned by
platform core position) to a bit mask used when targeting interrupts to
a PE, viz. when raising SGIs and routing SPIs.
The platform shall:
- Populate the driver data with a pointer to array that's to contain
per-PE target masks.
- Invoke the new driver API 'gicv2_set_pe_target_mask()' during
per-CPU initialization so that the driver populates the target mask
for that CPU.
Platforms that don't intend to target interrupts or raise SGIs need not
populate this.
Change-Id: Ic0db54da86915e9dccd82fff51479bc3c1fdc968
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'include/drivers/arm')
-rw-r--r-- | include/drivers/arm/gicv2.h | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h index 1ef0779b..c91cc1b0 100644 --- a/include/drivers/arm/gicv2.h +++ b/include/drivers/arm/gicv2.h @@ -13,6 +13,9 @@ /* Interrupt IDs reported by the HPPIR and IAR registers */ #define PENDING_G1_INTID 1022 +/* GICv2 can only target up to 8 PEs */ +#define GICV2_MAX_TARGET_PE 8 + /******************************************************************************* * GICv2 specific Distributor interface register offsets and constants. ******************************************************************************/ @@ -103,23 +106,29 @@ * in order to initialize the GICv2 driver. The attributes are described * below. * - * 1. The 'gicd_base' field contains the base address of the Distributor - * interface programmer's view. + * The 'gicd_base' field contains the base address of the Distributor interface + * programmer's view. + * + * The 'gicc_base' field contains the base address of the CPU Interface + * programmer's view. * - * 2. The 'gicc_base' field contains the base address of the CPU Interface - * programmer's view. + * The 'g0_interrupt_array' field is a pointer to an array in which each + * entry corresponds to an ID of a Group 0 interrupt. * - * 3. The 'g0_interrupt_array' field is a pointer to an array in which each - * entry corresponds to an ID of a Group 0 interrupt. + * The 'g0_interrupt_num' field contains the number of entries in the + * 'g0_interrupt_array'. * - * 4. The 'g0_interrupt_num' field contains the number of entries in the - * 'g0_interrupt_array'. + * The 'target_masks' is a pointer to an array containing 'target_masks_num' + * elements. The GIC driver will populate the array with per-PE target mask to + * use to when targeting interrupts. ******************************************************************************/ typedef struct gicv2_driver_data { uintptr_t gicd_base; uintptr_t gicc_base; unsigned int g0_interrupt_num; const unsigned int *g0_interrupt_array; + unsigned int *target_masks; + unsigned int target_masks_num; } gicv2_driver_data_t; /******************************************************************************* @@ -137,6 +146,7 @@ unsigned int gicv2_acknowledge_interrupt(void); void gicv2_end_of_interrupt(unsigned int id); unsigned int gicv2_get_interrupt_group(unsigned int id); unsigned int gicv2_get_running_priority(void); +void gicv2_set_pe_target_mask(unsigned int proc_num); #endif /* __ASSEMBLY__ */ #endif /* __GICV2_H__ */ |