diff options
| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-04-14 14:24:13 +0100 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-04-21 12:59:59 +0100 |
| commit | 072888656dc331c6b4bded88738e7b34166c0933 (patch) | |
| tree | 47243bfb790b50a76aa36b55949bdc8c1c631764 /include/lib/cpus | |
| parent | 0b77197baf9a22625f91112cf009c9209f4279e8 (diff) | |
Add support for Cortex-A57 erratum 826977 workaround
Change-Id: Icaacd19c4cef9c10d02adcc2f84a4d7c97d4bcfa
Diffstat (limited to 'include/lib/cpus')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 95c1f56c..685b87b2 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -62,6 +62,7 @@ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ #define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59) +#define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54) #define CPUACTLR_DIS_OVERREAD (1 << 52) #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) #define CPUACTLR_DCC_AS_DCCI (1 << 44) |