diff options
| author | Etienne Carriere <etienne.carriere@linaro.org> | 2017-11-05 22:56:03 +0100 |
|---|---|---|
| committer | Etienne Carriere <etienne.carriere@linaro.org> | 2017-11-08 13:49:36 +0100 |
| commit | 94f4700017bbcabc46d76c2d4fba24b9be73fa6c (patch) | |
| tree | f26344f1da7b8d7090f3124e738e5abab702d0cb /include/lib | |
| parent | 908cf7059795eee96e1120ecbedc13eae3d607aa (diff) | |
ARMv7 architecture have specific system registers
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/aarch32/arch.h | 16 | ||||
| -rw-r--r-- | include/lib/aarch32/arch_helpers.h | 8 |
2 files changed, 22 insertions, 2 deletions
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 3846bec4..c8940303 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -87,15 +87,21 @@ #define ID_PFR1_GIC_MASK 0xf /* SCTLR definitions */ -#define SCTLR_RES1 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \ - (1 << 3)) +#define SCTLR_RES1_DEF ((1 << 23) | (1 << 22) | (1 << 4) | (1 << 3)) +#if ARM_ARCH_MAJOR == 7 +#define SCTLR_RES1 SCTLR_RES1_DEF +#else +#define SCTLR_RES1 (SCTLR_RES1_DEF | (1 << 11)) +#endif #define SCTLR_M_BIT (1 << 0) #define SCTLR_A_BIT (1 << 1) #define SCTLR_C_BIT (1 << 2) #define SCTLR_CP15BEN_BIT (1 << 5) #define SCTLR_ITD_BIT (1 << 7) +#define SCTLR_Z_BIT (1 << 11) #define SCTLR_I_BIT (1 << 12) #define SCTLR_V_BIT (1 << 13) +#define SCTLR_RR_BIT (1 << 14) #define SCTLR_NTWI_BIT (1 << 16) #define SCTLR_NTWE_BIT (1 << 18) #define SCTLR_WXN_BIT (1 << 19) @@ -385,6 +391,7 @@ /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ #define SCR p15, 0, c1, c1, 0 #define SCTLR p15, 0, c1, c0, 0 +#define ACTLR p15, 0, c1, c0, 1 #define SDCR p15, 0, c1, c3, 1 #define MPIDR p15, 0, c0, c0, 5 #define MIDR p15, 0, c0, c0, 0 @@ -431,6 +438,11 @@ #define PMCR p15, 0, c9, c12, 0 #define CNTHP_CTL p15, 4, c14, c2, 1 +/* AArch32 coproc registers for 32bit MMU descriptor support */ +#define PRRR p15, 0, c10, c2, 0 +#define NMRR p15, 0, c10, c2, 1 +#define DACR p15, 0, c3, c0, 0 + /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ #define ICC_IAR1 p15, 0, c12, c12, 0 #define ICC_IAR0 p15, 0, c12, c8, 0 diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h index 469e9b0d..ede6d2ed 100644 --- a/include/lib/aarch32/arch_helpers.h +++ b/include/lib/aarch32/arch_helpers.h @@ -235,6 +235,7 @@ DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64) DEFINE_COPROCR_RW_FUNCS(scr, SCR) DEFINE_COPROCR_RW_FUNCS(ctr, CTR) DEFINE_COPROCR_RW_FUNCS(sctlr, SCTLR) +DEFINE_COPROCR_RW_FUNCS(actlr, ACTLR) DEFINE_COPROCR_RW_FUNCS(hsctlr, HSCTLR) DEFINE_COPROCR_RW_FUNCS(hcr, HCR) DEFINE_COPROCR_RW_FUNCS(hcptr, HCPTR) @@ -273,6 +274,13 @@ DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR) DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL) DEFINE_COPROCR_READ_FUNC(pmcr, PMCR) +DEFINE_COPROCR_RW_FUNCS(nsacr, NSACR) + +/* AArch32 coproc registers for 32bit MMU descriptor support */ +DEFINE_COPROCR_RW_FUNCS(prrr, PRRR) +DEFINE_COPROCR_RW_FUNCS(nmrr, NMRR) +DEFINE_COPROCR_RW_FUNCS(dacr, DACR) + /* * TLBI operation prototypes */ |