diff options
author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-05-26 14:15:40 +0100 |
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committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-08-01 14:33:47 +0100 |
commit | 1154586b71c1e0453076a50638f00d4499eb22b0 (patch) | |
tree | 46e9875d39a00bedbb07f575d5e9a28e707a6460 /include | |
parent | e33fd44548e41bcfa7bf697a36653e19e410e6c6 (diff) |
Add SMMUv3 driver
The driver has only one API: to initialize an SMMUv3 device. This
operates on a device that implements secure state, by invalidating
secure caches and TLBs.
Change-Id: Ief32800419ddf0f1fe38c8f0da8f5ba75c72c826
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/drivers/arm/smmu_v3.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/include/drivers/arm/smmu_v3.h b/include/drivers/arm/smmu_v3.h new file mode 100644 index 00000000..b7efde46 --- /dev/null +++ b/include/drivers/arm/smmu_v3.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SMMU_V3_H__ +#define __SMMU_V3_H__ + +#include <stdint.h> + +/* SMMUv3 register offsets from device base */ +#define SMMU_S_IDR1 0x8004 +#define SMMU_S_INIT 0x803c + +/* SMMU_S_IDR1 register fields */ +#define SMMU_S_IDR1_SECURE_IMPL_SHIFT 31 +#define SMMU_S_IDR1_SECURE_IMPL_MASK 0x1 + +/* SMMU_S_INIT register fields */ +#define SMMU_S_INIT_INV_ALL_MASK 0x1 + + +int smmuv3_init(uintptr_t smmu_base); + +#endif /* __SMMU_V3_H__ */ |