diff options
| author | David Cunado <david.cunado@arm.com> | 2016-11-25 00:21:59 +0000 |
|---|---|---|
| committer | David Cunado <david.cunado@arm.com> | 2016-12-01 16:17:39 +0000 |
| commit | 939f66d6c46a8fe8cac708ac8e52afea3ff7a095 (patch) | |
| tree | d010e8a900815c111ae190e9b9826e1f25764965 /include | |
| parent | c59428b1502f37c9b2f551613da1b491c4226d10 (diff) | |
Reset EL2 and EL3 configurable controls
This patch resets EL2 and EL3 registers that have architecturally
UNKNOWN values on reset and that also provide EL2/EL3 configuration
and trap controls.
Specifically, the EL2 physical timer is disabled to prevent timer
interrups into EL2 - CNTHP_CTL_EL2 and CNTHP_CTL for AArch64 and AArch32,
respectively.
Additionally, for AArch64, HSTR_EL2 is reset to avoid unexpected traps of
non-secure access to certain system registers at EL1 or lower.
For AArch32, the patch also reverts the reset to SDCR which was
incorrectly added in a previous change.
Change-Id: If00eaa23afa7dd36a922265194ccd6223187414f
Signed-off-by: David Cunado <david.cunado@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/common/aarch32/el3_common_macros.S | 8 | ||||
| -rw-r--r-- | include/lib/aarch32/arch.h | 2 | ||||
| -rw-r--r-- | include/lib/aarch32/arch_helpers.h | 1 | ||||
| -rw-r--r-- | include/lib/aarch64/arch_helpers.h | 2 |
4 files changed, 4 insertions, 9 deletions
diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S index 0018ea4b..50ce952f 100644 --- a/include/common/aarch32/el3_common_macros.S +++ b/include/common/aarch32/el3_common_macros.S @@ -67,14 +67,6 @@ orr r0, r0, #SCR_SIF_BIT stcopr r0, SCR - /* ----------------------------------------------------------------- - * Reset those registers that may have architecturally unknown reset - * values - * ----------------------------------------------------------------- - */ - mov r0, #0 - stcopr r0, SDCR - /* ----------------------------------------------------- * Enable the Asynchronous data abort now that the * exception vectors have been setup. diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 3c5ab26e..170fa841 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -382,8 +382,8 @@ /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ #define HDCR p15, 4, c1, c1, 1 -#define SDCR p15, 0, c1, c3, 1 #define PMCR p15, 0, c9, c12, 0 +#define CNTHP_CTL p15, 4, c14, c2, 1 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ #define ICC_IAR1 p15, 0, c12, c12, 0 diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h index 0633bca2..7955d62e 100644 --- a/include/lib/aarch32/arch_helpers.h +++ b/include/lib/aarch32/arch_helpers.h @@ -250,6 +250,7 @@ DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0) DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1) DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR) +DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL) DEFINE_COPROCR_READ_FUNC(pmcr, PMCR) /* diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index 37db0313..a013809b 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -280,6 +280,8 @@ DEFINE_SYSREG_READ_FUNC(isr_el1) DEFINE_SYSREG_READ_FUNC(ctr_el0) DEFINE_SYSREG_RW_FUNCS(mdcr_el2) +DEFINE_SYSREG_RW_FUNCS(hstr_el2) +DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2) DEFINE_SYSREG_READ_FUNC(pmcr_el0) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) |