diff options
| author | davidcunado-arm <david.cunado@arm.com> | 2017-09-13 14:52:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-09-13 14:52:24 +0100 |
| commit | f18f5f9867551d0d21da79e25371a298933aaff1 (patch) | |
| tree | 3f4c8c34f2cabb6defdab8389a592c9efe885a0c /include | |
| parent | a747b08e3a60800178a17cd6621dd5a6f27ae98c (diff) | |
| parent | 96ff26012fceab3e5e3b226cefdbedd0b294f312 (diff) | |
Merge pull request #1092 from jeenu-arm/errata-workarounds
Errata workarounds
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a57.h | 1 | ||||
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a72.h | 1 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 1 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a72.h | 1 |
4 files changed, 4 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index d3ae5b92..3fac9c7b 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -49,6 +49,7 @@ #define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) #define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) #define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38) +#define CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) #define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27) #define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25) #define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index 306253d5..f7da1f01 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -34,6 +34,7 @@ #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) /******************************************************************************* * L2 Control register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 070108d5..6c45c066 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -49,6 +49,7 @@ #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) +#define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index aed714c6..6fbb7076 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -34,6 +34,7 @@ #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) /******************************************************************************* * L2 Control register specific definitions. |