diff options
| author | Achin Gupta <achin.gupta@arm.com> | 2014-05-09 12:00:17 +0100 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2014-05-22 17:47:20 +0100 |
| commit | fa9c08b7d117cb736911288668f9fd987505b4e3 (patch) | |
| tree | c935c5a3ab474265b51c2b1c8c53ec798e9fee2c /include | |
| parent | dce74b891e0e6020d0a18384e32f280133631d9b (diff) | |
Use secure timer to generate S-EL1 interrupts
This patch adds support in the TSP to program the secure physical
generic timer to generate a EL-1 interrupt every half second. It also
adds support for maintaining the timer state across power management
operations. The TSPD ensures that S-EL1 can access the timer by
programming the SCR_EL3.ST bit.
This patch does not actually enable the timer. This will be done in a
subsequent patch once the complete framework for handling S-EL1
interrupts is in place.
Change-Id: I1b3985cfb50262f60824be3a51c6314ce90571bc
Diffstat (limited to 'include')
| -rw-r--r-- | include/bl32/payloads/tsp.h | 7 | ||||
| -rw-r--r-- | include/lib/aarch64/arch.h | 22 | ||||
| -rw-r--r-- | include/lib/aarch64/arch_helpers.h | 7 |
3 files changed, 36 insertions, 0 deletions
diff --git a/include/bl32/payloads/tsp.h b/include/bl32/payloads/tsp.h index 1f542d53..385d09c2 100644 --- a/include/bl32/payloads/tsp.h +++ b/include/bl32/payloads/tsp.h @@ -196,6 +196,13 @@ extern tsp_args_t *tsp_cpu_off_main(uint64_t arg0, uint64_t arg5, uint64_t arg6, uint64_t arg7); + +/* Generic Timer functions */ +extern void tsp_generic_timer_start(void); +extern void tsp_generic_timer_handler(void); +extern void tsp_generic_timer_stop(void); +extern void tsp_generic_timer_save(void); +extern void tsp_generic_timer_restore(void); #endif /* __ASSEMBLY__ */ #endif /* __BL2_H__ */ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 68bab36a..920dfc9b 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -265,6 +265,28 @@ ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) +/* Physical timer control register bit fields shifts and masks */ +#define CNTP_CTL_ENABLE_SHIFT 0 +#define CNTP_CTL_IMASK_SHIFT 1 +#define CNTP_CTL_ISTATUS_SHIFT 2 + +#define CNTP_CTL_ENABLE_MASK 1 +#define CNTP_CTL_IMASK_MASK 1 +#define CNTP_CTL_ISTATUS_MASK 1 + +#define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \ + CNTP_CTL_ENABLE_MASK) +#define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \ + CNTP_CTL_IMASK_MASK) +#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \ + CNTP_CTL_ISTATUS_MASK) + +#define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT) +#define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT) + +#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT)) +#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT)) + /* Miscellaneous MMU related constants */ #define NUM_2MB_IN_GB (1 << 9) #define NUM_4K_IN_2MB (1 << 9) diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index 0a398d08..f30301d1 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -202,6 +202,10 @@ extern unsigned long read_cptr_el3(void); extern unsigned long read_cpacr(void); extern unsigned long read_cpuectlr(void); extern unsigned int read_cntfrq_el0(void); +extern unsigned int read_cntps_ctl_el1(void); +extern unsigned int read_cntps_tval_el1(void); +extern unsigned long read_cntps_cval_el1(void); +extern unsigned long read_cntpct_el0(void); extern unsigned long read_cnthctl_el2(void); extern unsigned long read_tpidr_el3(void); @@ -210,6 +214,9 @@ extern void write_scr(unsigned long); extern void write_hcr(unsigned long); extern void write_cpacr(unsigned long); extern void write_cntfrq_el0(unsigned int); +extern void write_cntps_ctl_el1(unsigned int); +extern void write_cntps_tval_el1(unsigned int); +extern void write_cntps_cval_el1(unsigned long); extern void write_cnthctl_el2(unsigned long); extern void write_vbar_el1(unsigned long); |