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| author | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-05-16 09:59:54 +0100 |
|---|---|---|
| committer | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-06-08 11:46:31 +0100 |
| commit | d6b798097e23bc98814ced8406f4dc63df4078c5 (patch) | |
| tree | 548be6edab614effce85ce8f8c0090d245b1c541 /include | |
| parent | ee7cda31c759b39af7487ddd5ab799208f288c03 (diff) | |
Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76
The Cortex-A76 implements SMCCC_ARCH_WORKAROUND_2 as defined in
"Firmware interfaces for mitigating cache speculation vulnerabilities
System Software on Arm Systems"[0].
Dynamic mitigation for CVE-2018-3639 is enabled/disabled by
setting/clearning bit 16 (Disable load pass store) of `CPUACTLR2_EL1`.
NOTE: The generic code that implements dynamic mitigation does not
currently implement the expected semantics when dispatching an SDEI
event to a lower EL. This will be fixed in a separate patch.
[0] https://developer.arm.com/cache-speculation-vulnerability-firmware-specification
Change-Id: I8fb2862b9ab24d55a0e9693e48e8be4df32afb5a
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a76.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index de6288d8..1cb77476 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -16,6 +16,13 @@ #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 + +#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (1 << 16) + /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ #define CORTEX_A76_CORE_PWRDN_EN_MASK 0x1 |