diff options
author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-04-14 13:32:31 +0100 |
---|---|---|
committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-04-21 09:44:51 +0100 |
commit | df22d602b6b1ee00a0cb31e88bb63e7152f2cf6a (patch) | |
tree | 75145b1bc05af5e40dc3924f5c2658cf1acaf623 /lib/cpus/aarch64 | |
parent | 097b787a0e6dc65ff4bf7c6e1da966858036e22a (diff) |
Add support for Cortex-A57 erratum 826974 workaround
Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4
Diffstat (limited to 'lib/cpus/aarch64')
-rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 4c0b8ce3..d992f98b 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -167,6 +167,33 @@ disable_hint: ret endfunc a57_disable_ldnp_overread + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #826974. + * This applies only to revision <= r1p1 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_826974_wa + /* + * Compare x0 against revision r1p1 + */ + cmp x0, #0x11 + b.ls apply_826974 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_826974: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_826974_wa + + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. * Clobbers: x0-x5, x15, x19, x30 @@ -200,6 +227,11 @@ func cortex_a57_reset_func bl a57_disable_ldnp_overread #endif +#if ERRATA_A57_826974 + mov x0, x15 + bl errata_a57_826974_wa +#endif + /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- |