diff options
| author | davidcunado-arm <david.cunado@arm.com> | 2017-12-04 22:39:40 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-12-04 22:39:40 +0000 |
| commit | a852ec46055977c2cd811d5b54eb3044858fe2ee (patch) | |
| tree | 9bb753e56d28ca41c9cf7333c86d7690603741be /lib/cpus | |
| parent | 5627c1ed9ed7b1ce70355dc2dea1dbf7a697f3e1 (diff) | |
| parent | 5f70d8de5b696a7b21284d96839caa981c8fdf30 (diff) | |
Merge pull request #1168 from matt2048/master
Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONS
Diffstat (limited to 'lib/cpus')
| -rw-r--r-- | lib/cpus/aarch32/cortex_a53.S | 4 | ||||
| -rw-r--r-- | lib/cpus/aarch32/cortex_a57.S | 4 | ||||
| -rw-r--r-- | lib/cpus/aarch32/cortex_a72.S | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S index 74cedc35..1647e169 100644 --- a/lib/cpus/aarch32/cortex_a53.S +++ b/lib/cpus/aarch32/cortex_a53.S @@ -174,7 +174,7 @@ func cortex_a53_core_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) @@ -204,7 +204,7 @@ func cortex_a53_cluster_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S index b5189e77..64a6d674 100644 --- a/lib/cpus/aarch32/cortex_a57.S +++ b/lib/cpus/aarch32/cortex_a57.S @@ -406,7 +406,7 @@ func cortex_a57_core_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) @@ -448,7 +448,7 @@ func cortex_a57_cluster_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) diff --git a/lib/cpus/aarch32/cortex_a72.S b/lib/cpus/aarch32/cortex_a72.S index 69cc2ea5..75505206 100644 --- a/lib/cpus/aarch32/cortex_a72.S +++ b/lib/cpus/aarch32/cortex_a72.S @@ -120,7 +120,7 @@ func cortex_a72_core_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) @@ -167,7 +167,7 @@ func cortex_a72_cluster_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) |