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author | Etienne Carriere <etienne.carriere@linaro.org> | 2017-09-01 10:22:20 +0200 |
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committer | Etienne Carriere <etienne.carriere@linaro.org> | 2017-09-01 10:22:20 +0200 |
commit | 86606eb51e81b4189579e2b429f1c8f26f5c804c (patch) | |
tree | ac4535b711a6744398802de913fc43a678090b95 /lib/el3_runtime/aarch32 | |
parent | 096b7af7c93953673c0500156f482ad8c6da525e (diff) |
cpu log buffer size depends on cache line size
Platform may use specific cache line sizes. Since CACHE_WRITEBACK_GRANULE
defines the platform specific cache line size, it is used to define the
size of the cpu data structure CPU_DATA_SIZE aligned on cache line size.
Introduce assembly macro 'mov_imm' for AArch32 to simplify implementation
of function '_cpu_data_by_index'.
Change-Id: Ic2d49ffe0c3e51649425fd9c8c99559c582ac5a1
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Diffstat (limited to 'lib/el3_runtime/aarch32')
-rw-r--r-- | lib/el3_runtime/aarch32/cpu_data.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/el3_runtime/aarch32/cpu_data.S b/lib/el3_runtime/aarch32/cpu_data.S index 3d6b8069..68d64151 100644 --- a/lib/el3_runtime/aarch32/cpu_data.S +++ b/lib/el3_runtime/aarch32/cpu_data.S @@ -34,7 +34,9 @@ endfunc _cpu_data * ----------------------------------------------------------------- */ func _cpu_data_by_index + mov_imm r1, CPU_DATA_SIZE + mul r0, r0, r1 ldr r1, =percpu_data - add r0, r1, r0, LSL #CPU_DATA_LOG2SIZE + add r0, r0, r1 bx lr endfunc _cpu_data_by_index |