diff options
| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2018-09-04 17:49:32 +0530 |
|---|---|---|
| committer | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2018-09-04 17:49:32 +0530 |
| commit | 6a0f7c0077983f1f56b4214f05a22fb93beb9593 (patch) | |
| tree | 9ebef5b241db7c0225781283dc019cbb8fe9beaf /lib/libc/printf.c | |
| parent | 26a754f6ad41a4dc5e5b84233cb5eba1de59c4a3 (diff) | |
zynqmp: pm_service: Ignore enable/disable of PLL type clocks
PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable
them based on their user count. So, it should not be handled from ATF.
Put PLL type clock into bypass and reset mode only while changing
PLL rate (FBDIV).
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Diffstat (limited to 'lib/libc/printf.c')
0 files changed, 0 insertions, 0 deletions