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| author | danh-arm <dan.handley@arm.com> | 2016-12-20 12:27:58 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-12-20 12:27:58 +0000 |
| commit | 67748e4827976f3b13f8bc1281b3c4b59da87e4a (patch) | |
| tree | 1d1c8fcb43ebe67ba45cc334fd0ea6e58f09e335 /lib/psci/aarch32/psci_helpers.S | |
| parent | 9acdafbccf730179406ce7693772d7f7dcc4ae3c (diff) | |
| parent | 5dd9dbb5bfe64b1eb2e78648f3a2e900678ef433 (diff) | |
Merge pull request #788 from jeenu-arm/cpuops-framework
Add provision to extend CPU operations at more levels
Diffstat (limited to 'lib/psci/aarch32/psci_helpers.S')
| -rw-r--r-- | lib/psci/aarch32/psci_helpers.S | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/lib/psci/aarch32/psci_helpers.S b/lib/psci/aarch32/psci_helpers.S index 5a41ff31..9f991dfe 100644 --- a/lib/psci/aarch32/psci_helpers.S +++ b/lib/psci/aarch32/psci_helpers.S @@ -65,22 +65,13 @@ func psci_do_pwrdown_cache_maintenance bl do_stack_maintenance /* --------------------------------------------- - * Determine how many levels of cache will be - * subject to cache maintenance. Power level - * 0 implies that only the cpu is being powered - * down. Only the L1 data cache needs to be - * flushed to the PoU in this case. For a higher - * power level we are assuming that a flush - * of L1 data and L2 unified cache is enough. - * This information should be provided by the - * platform. + * Invoke CPU-specifc power down operations for + * the appropriate level * --------------------------------------------- */ - cmp r4, #PSCI_CPU_PWR_LVL - pop {r4,lr} - - beq prepare_core_pwr_dwn - b prepare_cluster_pwr_dwn + mov r0, r4 + pop {r4, lr} + b prepare_cpu_pwr_dwn endfunc psci_do_pwrdown_cache_maintenance |