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| author | Nishanth Menon <nm@ti.com> | 2017-01-10 09:34:07 -0600 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2017-01-10 09:36:44 -0600 |
| commit | 861ac52a7e80c0399b6e543e7125a9c1e18a63f8 (patch) | |
| tree | 4d735faceb0449e4de072adc56e60e88d105a69f /lib/psci/psci_main.c | |
| parent | 176129530e80491a789ea6402a18b65834c7fe54 (diff) | |
uart: 16550: Fix getc
tbz check for RDR status is to check for a bit being zero.
Unfortunately, we are using a mask rather than the bit position.
Further as per http://www.ti.com/lit/ds/symlink/pc16550d.pdf (page 17),
LSR register bit 0 is Data ready status (RDR), not bit position 2.
Update the same to match the specification.
Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'lib/psci/psci_main.c')
0 files changed, 0 insertions, 0 deletions