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| author | Varun Wadekar <vwadekar@nvidia.com> | 2018-01-10 17:03:22 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2018-05-15 15:53:50 -0700 |
| commit | b0301467bc25151e4c2180b1e1e5dee3bdad963e (patch) | |
| tree | 65291781470f3b468638ac0f3dc334ef7b715d2b /lib/psci/psci_private.h | |
| parent | 885ca54a75e14a63c375b5d12852dc7ef2c0b568 (diff) | |
Workaround for CVE-2017-5715 on NVIDIA Denver CPUs
Flush the indirect branch predictor and RSB on entry to EL3 by issuing
a newly added instruction for Denver CPUs. Support for this operation
can be determined by comparing bits 19:16 of ID_AFR0_EL1 with 0b0001.
To achieve this without performing any branch instruction, a per-cpu
vbar is installed which executes the workaround and then branches off
to the corresponding vector entry in the main vector table. A side
effect of this change is that the main vbar is configured before any
reset handling. This is to allow the per-cpu reset function to override
the vbar setting.
Change-Id: Ief493cd85935bab3cfee0397e856db5101bc8011
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'lib/psci/psci_private.h')
0 files changed, 0 insertions, 0 deletions