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| author | Marcin Wojtas <mw@semihalf.com> | 2018-03-21 09:55:47 +0100 |
|---|---|---|
| committer | Konstantin Porotchkin <kostap@marvell.com> | 2018-09-03 15:46:14 +0300 |
| commit | 4acd900df6275cd724266157e04e2b75d82cf24a (patch) | |
| tree | aacd6b760a02e7deab2a8c9972b9d09b1238dfe9 /lib/psci/psci_stat.c | |
| parent | 155d01ff1eea98fbec128688eedbefc8a6b798af (diff) | |
gicv2: enable configuring IRQ trigger type
This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful to modify
the default configuration of the non-secure GIC SPI's, which
are all set during initialization to be level-sensitive.
Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'lib/psci/psci_stat.c')
0 files changed, 0 insertions, 0 deletions