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authorJeenu Viswambharan <jeenu.viswambharan@arm.com>2016-11-18 12:58:28 +0000
committerJeenu Viswambharan <jeenu.viswambharan@arm.com>2016-12-15 15:41:40 +0000
commit5dd9dbb5bfe64b1eb2e78648f3a2e900678ef433 (patch)
tree14340eb6c21aafc10aac402cf0ca6f7d2efc28c2 /lib/psci
parenta4af0c2e8409696667695f3781a22cba2eafbd2c (diff)
Add provision to extend CPU operations at more levels
Various CPU drivers in ARM Trusted Firmware register functions to handle power-down operations. At present, separate functions are registered to power down individual cores and clusters. This scheme operates on the basis of core and cluster, and doesn't cater for extending the hierarchy for power-down operations. For example, future CPUs might support multiple threads which might need powering down individually. This patch therefore reworks the CPU operations framework to allow for registering power down handlers on specific level basis. Henceforth: - Generic code invokes CPU power down operations by the level required. - CPU drivers explicitly mention CPU_NO_RESET_FUNC when the CPU has no reset function. - CPU drivers register power down handlers as a list: a mandatory handler for level 0, and optional handlers for higher levels. All existing CPU drivers are adapted to the new CPU operations framework without needing any functional changes within. Also update firmware design guide. Change-Id: I1826842d37a9e60a9e85fdcee7b4b8f6bc1ad043 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'lib/psci')
-rw-r--r--lib/psci/aarch32/psci_helpers.S19
-rw-r--r--lib/psci/aarch64/psci_helpers.S20
2 files changed, 8 insertions, 31 deletions
diff --git a/lib/psci/aarch32/psci_helpers.S b/lib/psci/aarch32/psci_helpers.S
index 5a41ff31..9f991dfe 100644
--- a/lib/psci/aarch32/psci_helpers.S
+++ b/lib/psci/aarch32/psci_helpers.S
@@ -65,22 +65,13 @@ func psci_do_pwrdown_cache_maintenance
bl do_stack_maintenance
/* ---------------------------------------------
- * Determine how many levels of cache will be
- * subject to cache maintenance. Power level
- * 0 implies that only the cpu is being powered
- * down. Only the L1 data cache needs to be
- * flushed to the PoU in this case. For a higher
- * power level we are assuming that a flush
- * of L1 data and L2 unified cache is enough.
- * This information should be provided by the
- * platform.
+ * Invoke CPU-specifc power down operations for
+ * the appropriate level
* ---------------------------------------------
*/
- cmp r4, #PSCI_CPU_PWR_LVL
- pop {r4,lr}
-
- beq prepare_core_pwr_dwn
- b prepare_cluster_pwr_dwn
+ mov r0, r4
+ pop {r4, lr}
+ b prepare_cpu_pwr_dwn
endfunc psci_do_pwrdown_cache_maintenance
diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S
index eaa17c72..108f0687 100644
--- a/lib/psci/aarch64/psci_helpers.S
+++ b/lib/psci/aarch64/psci_helpers.S
@@ -59,24 +59,11 @@ func psci_do_pwrdown_cache_maintenance
stp x19, x20, [sp,#-16]!
/* ---------------------------------------------
- * Determine to how many levels of cache will be
- * subject to cache maintenance. Power level
- * 0 implies that only the cpu is being powered
- * down. Only the L1 data cache needs to be
- * flushed to the PoU in this case. For a higher
- * power level we are assuming that a flush
- * of L1 data and L2 unified cache is enough.
- * This information should be provided by the
- * platform.
+ * Invoke CPU-specific power down operations for
+ * the appropriate level
* ---------------------------------------------
*/
- cmp w0, #PSCI_CPU_PWR_LVL
- b.eq do_core_pwr_dwn
- bl prepare_cluster_pwr_dwn
- b do_stack_maintenance
-
-do_core_pwr_dwn:
- bl prepare_core_pwr_dwn
+ bl prepare_cpu_pwr_dwn
/* ---------------------------------------------
* Do stack maintenance by flushing the used
@@ -84,7 +71,6 @@ do_core_pwr_dwn:
* remainder.
* ---------------------------------------------
*/
-do_stack_maintenance:
bl plat_get_my_stack
/* ---------------------------------------------