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| author | Xing Zheng <zhengxing@rock-chips.com> | 2016-12-22 18:34:14 +0800 |
|---|---|---|
| committer | Xing Zheng <zhengxing@rock-chips.com> | 2017-02-24 20:07:44 +0800 |
| commit | ae7a93521fd46f278a35d847a83e621026a33786 (patch) | |
| tree | 60b2e156b4cf78088c48393d00839e9b215d6f7c /lib/psci | |
| parent | 941c71475e1b7a3ac41e61aac1ed5d3b7304b59b (diff) | |
rockchip: rk3399: sperate the BL31 parameters for sharing
Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE
and TZRAM_SIZE for DDR secure regions), we can split them and don't have
to hardcode the range in two places.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Diffstat (limited to 'lib/psci')
0 files changed, 0 insertions, 0 deletions