diff options
| author | Derek Basehore <dbasehore@chromium.org> | 2017-02-09 22:02:42 -0800 |
|---|---|---|
| committer | Xing Zheng <zhengxing@rock-chips.com> | 2017-02-24 20:07:45 +0800 |
| commit | 5a5dc61713fd563a3bb8a89bd26729f4348bb5d6 (patch) | |
| tree | 9b65ed64df3530d3d33aca4274df3da604fb2d81 /lib/stdlib/assert.c | |
| parent | 43f52e92e45823c6967b20fb9e90dd6e3dc7275f (diff) | |
rockchip: rk3399: Fix CAS latency setting
The F1 CAS latency setting was not bit shifted, which resulted in
setting the DRAM additive latency value instead.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Diffstat (limited to 'lib/stdlib/assert.c')
0 files changed, 0 insertions, 0 deletions