diff options
| author | David Cunado <david.cunado@arm.com> | 2016-11-25 00:21:59 +0000 |
|---|---|---|
| committer | David Cunado <david.cunado@arm.com> | 2016-12-01 16:17:39 +0000 |
| commit | 939f66d6c46a8fe8cac708ac8e52afea3ff7a095 (patch) | |
| tree | d010e8a900815c111ae190e9b9826e1f25764965 /lib | |
| parent | c59428b1502f37c9b2f551613da1b491c4226d10 (diff) | |
Reset EL2 and EL3 configurable controls
This patch resets EL2 and EL3 registers that have architecturally
UNKNOWN values on reset and that also provide EL2/EL3 configuration
and trap controls.
Specifically, the EL2 physical timer is disabled to prevent timer
interrups into EL2 - CNTHP_CTL_EL2 and CNTHP_CTL for AArch64 and AArch32,
respectively.
Additionally, for AArch64, HSTR_EL2 is reset to avoid unexpected traps of
non-secure access to certain system registers at EL1 or lower.
For AArch32, the patch also reverts the reset to SDCR which was
incorrectly added in a previous change.
Change-Id: If00eaa23afa7dd36a922265194ccd6223187414f
Signed-off-by: David Cunado <david.cunado@arm.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/el3_runtime/aarch32/context_mgmt.c | 6 | ||||
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 12 |
2 files changed, 18 insertions, 0 deletions
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c index 29532e8c..51b77595 100644 --- a/lib/el3_runtime/aarch32/context_mgmt.c +++ b/lib/el3_runtime/aarch32/context_mgmt.c @@ -243,6 +243,12 @@ void cm_prepare_el3_exit(uint32_t security_state) * (5 bits) and HPMN is at offset zero within HDCR. */ write_hdcr((read_pmcr() & PMCR_N_BITS) >> PMCR_N_SHIFT); + + /* + * Reset CNTHP_CTL to disable the EL2 physical timer and + * therefore prevent timer interrupts. + */ + write_cnthp_ctl(0); isb(); write_scr(read_scr() & ~SCR_NS_BIT); diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index fadc1dbf..35380f36 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -269,6 +269,18 @@ void cm_prepare_el3_exit(uint32_t security_state) */ write_mdcr_el2((read_pmcr_el0() & PMCR_EL0_N_BITS) >> PMCR_EL0_N_SHIFT); + /* + * Avoid unexpected traps of non-secure access to + * certain system registers at EL1 or lower where + * HSTR_EL2 is not completely reset to zero by the + * hardware - zero the entire register. + */ + write_hstr_el2(0); + /* + * Reset CNTHP_CTL_EL2 to disable the EL2 physical timer + * and therefore prevent timer interrupts. + */ + write_cnthp_ctl_el2(0); } } |