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| author | davidcunado-arm <david.cunado@arm.com> | 2017-03-20 12:25:08 +0000 | 
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-03-20 12:25:08 +0000 | 
| commit | 6db7190b2c0b1e7f8559e4a7d4f4d904913e3709 (patch) | |
| tree | 8c048546225d0bfa7a48f77dd61f4ea5f9b6f7dc /lib | |
| parent | 3944adca5943a050ca7e7e9cc802a9ae04dec186 (diff) | |
| parent | baac5dd4cf4a5dbaf692583c47d3439054cbbd5d (diff) | |
Merge pull request #857 from Andre-ARM/a53-855873
ARM Cortex-A53 erratum 855873 workaround
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 43 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cpu_helpers.S | 14 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 10 | 
3 files changed, 66 insertions, 1 deletions
| diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index 1dd8a865..a36666bc 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -129,6 +129,39 @@ func check_errata_disable_non_temporal_hint  	b	cpu_rev_var_ls  endfunc check_errata_disable_non_temporal_hint +	/* -------------------------------------------------- +	 * Errata Workaround for Cortex A53 Errata #855873. +	 * +	 * This applies only to revisions >= r0p3 of Cortex A53. +	 * Earlier revisions of the core are affected as well, but don't +	 * have the chicken bit in the CPUACTLR register. It is expected that +	 * the rich OS takes care of that, especially as the workaround is +	 * shared with other erratas in those revisions of the CPU. +	 * Inputs: +	 * x0: variant[4:7] and revision[0:3] of current cpu. +	 * Shall clobber: x0-x17 +	 * -------------------------------------------------- +	 */ +func errata_a53_855873_wa +	/* +	 * Compare x0 against revision r0p3 and higher +	 */ +        mov     x17, x30 +        bl      check_errata_855873 +        cbz     x0, 1f + +	mrs	x1, CPUACTLR_EL1 +	orr	x1, x1, #CPUACTLR_ENDCCASCI +	msr	CPUACTLR_EL1, x1 +1: +	ret	x17 +endfunc errata_a53_855873_wa + +func check_errata_855873 +	mov	x1, #0x03 +	b	cpu_rev_var_hs +endfunc check_errata_855873 +  	/* -------------------------------------------------  	 * The CPU Ops reset function for Cortex-A53.  	 * Shall clobber: x0-x19 @@ -150,6 +183,11 @@ func cortex_a53_reset_func  	bl	a53_disable_non_temporal_hint  #endif +#if ERRATA_A53_855873 +	mov	x0, x18 +	bl	errata_a53_855873_wa +#endif +  	/* ---------------------------------------------  	 * Enable the SMP bit.  	 * --------------------------------------------- @@ -238,6 +276,7 @@ func cortex_a53_errata_report  	 */  	report_errata ERRATA_A53_826319, cortex_a53, 826319  	report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint +	report_errata ERRATA_A53_855873, cortex_a53, 855873  	ldp	x8, x30, [sp], #16  	ret @@ -255,13 +294,15 @@ endfunc cortex_a53_errata_report  	 */  .section .rodata.cortex_a53_regs, "aS"  cortex_a53_regs:  /* The ascii list of register names to be reported */ -	.asciz	"cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" +	.asciz	"cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ +		"cpuactlr_el1", ""  func cortex_a53_cpu_reg_dump  	adr	x6, cortex_a53_regs  	mrs	x8, CPUECTLR_EL1  	mrs	x9, CPUMERRSR_EL1  	mrs	x10, L2MERRSR_EL1 +	mrs	x11, CPUACTLR_EL1  	ret  endfunc cortex_a53_cpu_reg_dump diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index 6a3669de..47cb6a2d 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -234,6 +234,20 @@ func cpu_rev_var_ls  	ret  endfunc cpu_rev_var_ls +/* + * Compare the CPU's revision-variant (x0) with a given value (x1), for errata + * application purposes. If the revision-variant is higher than or same as a + * given value, indicates that errata applies; otherwise not. + */ +	.globl	cpu_rev_var_hs +func cpu_rev_var_hs +	mov	x2, #ERRATA_APPLIES +	mov	x3, #ERRATA_NOT_APPLIES +	cmp	x0, x1 +	csel	x0, x2, x3, hs +	ret +endfunc cpu_rev_var_hs +  #if REPORT_ERRATA  /*   * void print_errata_status(void); diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 7d7db203..132ab6f7 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -66,6 +66,12 @@ ERRATA_A53_826319	?=0  # erratum workaround is enabled by default in hardware.  ERRATA_A53_836870	?=0 +# Flag to apply errata 855873 during reset. This errata applies to all +# revisions of the Cortex A53 CPU, but this firmware workaround only works +# for revisions r0p3 and higher. Earlier revisions are taken care +# of by the rich OS. +ERRATA_A53_855873	?=0 +  # Flag to apply erratum 806969 workaround during reset. This erratum applies  # only to revision r0p0 of the Cortex A57 cpu.  ERRATA_A57_806969	?=0 @@ -106,6 +112,10 @@ $(eval $(call add_define,ERRATA_A53_826319))  $(eval $(call assert_boolean,ERRATA_A53_836870))  $(eval $(call add_define,ERRATA_A53_836870)) +# Process ERRATA_A53_855873 flag +$(eval $(call assert_boolean,ERRATA_A53_855873)) +$(eval $(call add_define,ERRATA_A53_855873)) +  # Process ERRATA_A57_806969 flag  $(eval $(call assert_boolean,ERRATA_A57_806969))  $(eval $(call add_define,ERRATA_A57_806969)) | 
