diff options
| author | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-07-11 14:22:22 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-11 14:22:22 +0100 |
| commit | df4c512d470d8bb728343b7edf040ce7c515bd79 (patch) | |
| tree | 44a0d75ddda315f2131f392cecc10f103ce46481 /lib | |
| parent | 6cbf17d11404319d79981b8566c15407cb86eefa (diff) | |
| parent | 46e88703852958f9a212080724f2c6fdfb21fa1c (diff) | |
Merge pull request #1474 from dp-arm/dp/cpus
Add initial CPU support for Cortex-Deimos and Cortex-Helios
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_deimos.S | 51 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_helios.S | 34 |
2 files changed, 85 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_deimos.S b/lib/cpus/aarch64/cortex_deimos.S new file mode 100644 index 00000000..aec62a28 --- /dev/null +++ b/lib/cpus/aarch64/cortex_deimos.S @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <bl_common.h> +#include <cortex_deimos.h> +#include <cpu_macros.S> +#include <plat_macros.S> + + /* --------------------------------------------- + * HW will do the cache maintenance while powering down + * --------------------------------------------- + */ +func cortex_deimos_core_pwr_dwn + /* --------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------- + */ + mrs x0, CORTEX_DEIMOS_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_DEIMOS_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_deimos_core_pwr_dwn + + /* --------------------------------------------- + * This function provides Cortex-Deimos specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_deimos_regs, "aS" +cortex_deimos_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_deimos_cpu_reg_dump + adr x6, cortex_deimos_regs + mrs x8, CORTEX_DEIMOS_CPUECTLR_EL1 + ret +endfunc cortex_deimos_cpu_reg_dump + +declare_cpu_ops cortex_deimos, CORTEX_DEIMOS_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_deimos_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_helios.S b/lib/cpus/aarch64/cortex_helios.S new file mode 100644 index 00000000..bcda7411 --- /dev/null +++ b/lib/cpus/aarch64/cortex_helios.S @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arch.h> +#include <asm_macros.S> +#include <bl_common.h> +#include <cortex_helios.h> +#include <cpu_macros.S> +#include <debug.h> +#include <plat_macros.S> + +func cortex_helios_cpu_pwr_dwn + mrs x0, CORTEX_HELIOS_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_HELIOS_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_helios_cpu_pwr_dwn + +.section .rodata.cortex_helios_regs, "aS" +cortex_helios_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_helios_cpu_reg_dump + adr x6, cortex_helios_regs + mrs x8, CORTEX_HELIOS_ECTLR_EL1 + ret +endfunc cortex_helios_cpu_reg_dump + +declare_cpu_ops cortex_helios, CORTEX_HELIOS_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_helios_cpu_pwr_dwn |