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| author | Etienne Carriere <etienne.carriere@linaro.org> | 2017-09-01 10:22:20 +0200 |
|---|---|---|
| committer | Etienne Carriere <etienne.carriere@linaro.org> | 2017-09-01 10:22:20 +0200 |
| commit | 86606eb51e81b4189579e2b429f1c8f26f5c804c (patch) | |
| tree | ac4535b711a6744398802de913fc43a678090b95 /maintainers.rst | |
| parent | 096b7af7c93953673c0500156f482ad8c6da525e (diff) | |
cpu log buffer size depends on cache line size
Platform may use specific cache line sizes. Since CACHE_WRITEBACK_GRANULE
defines the platform specific cache line size, it is used to define the
size of the cpu data structure CPU_DATA_SIZE aligned on cache line size.
Introduce assembly macro 'mov_imm' for AArch32 to simplify implementation
of function '_cpu_data_by_index'.
Change-Id: Ic2d49ffe0c3e51649425fd9c8c99559c582ac5a1
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Diffstat (limited to 'maintainers.rst')
0 files changed, 0 insertions, 0 deletions