diff options
author | davidcunado-arm <david.cunado@arm.com> | 2017-10-21 22:50:35 +0100 |
---|---|---|
committer | GitHub <noreply@github.com> | 2017-10-21 22:50:35 +0100 |
commit | f911e229f3ab0481230cf1e03bc0c076707c9567 (patch) | |
tree | ef467e5d6a214509cd786bdd5346c6d21210eaf9 /plat/arm | |
parent | 623c43774a2d1c923a6d886da34dbb78fcac62a4 (diff) | |
parent | 95ad62b2c21a0ec5e847207f7c70919a40b56110 (diff) |
Merge pull request #1131 from jeenu-arm/gic-migrate
Migrate upstream platforms to using interrupt properties
Diffstat (limited to 'plat/arm')
-rw-r--r-- | plat/arm/board/fvp/include/platform_def.h | 9 | ||||
-rw-r--r-- | plat/arm/board/juno/include/platform_def.h | 38 | ||||
-rw-r--r-- | plat/arm/common/arm_gicv2.c | 10 | ||||
-rw-r--r-- | plat/arm/common/arm_gicv3.c | 18 |
4 files changed, 41 insertions, 34 deletions
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index e4f94259..e9535803 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -136,4 +136,13 @@ #define PLAT_ARM_G0_IRQS ARM_G0_IRQS +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 3c44a1e9..395d1fb6 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -193,23 +193,27 @@ */ #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000 -/* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ - ARM_G1S_IRQS, \ - JUNO_IRQ_DMA_SMMU, \ - JUNO_IRQ_HDLCD0_SMMU, \ - JUNO_IRQ_HDLCD1_SMMU, \ - JUNO_IRQ_USB_SMMU, \ - JUNO_IRQ_THIN_LINKS_SMMU, \ - JUNO_IRQ_SEC_I2C, \ - JUNO_IRQ_GPU_SMMU_1, \ - JUNO_IRQ_ETR_SMMU - -#define PLAT_ARM_G0_IRQS ARM_G0_IRQS +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + CSS_G1S_IRQ_PROPS(grp), \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) /* * Required ARM CSS SoC based platform porting definitions diff --git a/plat/arm/common/arm_gicv2.c b/plat/arm/common/arm_gicv2.c index 6dd847b2..aac0248c 100644 --- a/plat/arm/common/arm_gicv2.c +++ b/plat/arm/common/arm_gicv2.c @@ -23,9 +23,9 @@ * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 * interrupts. *****************************************************************************/ -static const unsigned int g0_interrupt_array[] = { - PLAT_ARM_G1S_IRQS, - PLAT_ARM_G0_IRQS +static const interrupt_prop_t arm_interrupt_props[] = { + PLAT_ARM_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), + PLAT_ARM_G0_IRQ_PROPS(GICV2_INTR_GROUP0) }; static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; @@ -33,8 +33,8 @@ static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; static const gicv2_driver_data_t arm_gic_data = { .gicd_base = PLAT_ARM_GICD_BASE, .gicc_base = PLAT_ARM_GICC_BASE, - .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), - .g0_interrupt_array = g0_interrupt_array, + .interrupt_props = arm_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), .target_masks = target_mask_array, .target_masks_num = ARRAY_SIZE(target_mask_array), }; diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index c9bba095..cec6a9df 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -6,6 +6,7 @@ #include <arm_def.h> #include <gicv3.h> +#include <interrupt_props.h> #include <plat_arm.h> #include <platform.h> #include <platform_def.h> @@ -25,14 +26,9 @@ /* The GICv3 driver only needs to be initialized in EL3 */ static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; -/* Array of Group1 secure interrupts to be configured by the gic driver */ -static const unsigned int g1s_interrupt_array[] = { - PLAT_ARM_G1S_IRQS -}; - -/* Array of Group0 interrupts to be configured by the gic driver */ -static const unsigned int g0_interrupt_array[] = { - PLAT_ARM_G0_IRQS +static const interrupt_prop_t arm_interrupt_props[] = { + PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), + PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0) }; /* @@ -58,10 +54,8 @@ static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr) const gicv3_driver_data_t arm_gic_data = { .gicd_base = PLAT_ARM_GICD_BASE, .gicr_base = PLAT_ARM_GICR_BASE, - .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), - .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), - .g0_interrupt_array = g0_interrupt_array, - .g1s_interrupt_array = g1s_interrupt_array, + .interrupt_props = arm_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props), .rdistif_num = PLATFORM_CORE_COUNT, .rdistif_base_addrs = rdistif_base_addrs, .mpidr_to_core_pos = arm_gicv3_mpidr_hash |