diff options
author | Olivier Masse <olivier.masse@nxp.com> | 2018-09-25 15:59:35 +0200 |
---|---|---|
committer | Olivier Masse <olivier.masse@nxp.com> | 2018-11-13 15:15:59 +0100 |
commit | ac0b499ff6618e0bb4d0cdb55009f75c914d4fe7 (patch) | |
tree | c3b3ce4c548dac49bb952f251557f8fba9b92edf /plat/imx/imx8mm | |
parent | 2fb1862f155399cfb939bb35cf94e249b76ce74f (diff) |
MMIOT-152 Rebase on imx_1.5.y + imx8mm : DRM RDC config added
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
Diffstat (limited to 'plat/imx/imx8mm')
-rw-r--r-- | plat/imx/imx8mm/imx8mm_bl31_setup.c | 75 | ||||
-rw-r--r-- | plat/imx/imx8mm/platform.mk | 16 |
2 files changed, 90 insertions, 1 deletions
diff --git a/plat/imx/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8mm/imx8mm_bl31_setup.c index 9b3145c4..cc7e15ed 100644 --- a/plat/imx/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8mm/imx8mm_bl31_setup.c @@ -66,6 +66,70 @@ extern unsigned long __COHERENT_RAM_END__; static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; +#define IMX_DDR_BASE 0x40000000 + +#if defined(DECRYPTED_BUFFER_START) && defined(DECRYPTED_BUFFER_LEN) +#define DECRYPTED_BUFFER_END DECRYPTED_BUFFER_START + DECRYPTED_BUFFER_LEN +#endif + +#if defined(DECODED_BUFFER_START) && defined(DECODED_BUFFER_LEN) +#define DECODED_BUFFER_END DECODED_BUFFER_START + DECODED_BUFFER_LEN +#endif + +#if !defined(DECRYPTED_BUFFER_END) && !defined(DECODED_BUFFER_END) +#define RDC_DISABLED +#endif + +/* set RDC settings */ +static void bl31_imx_rdc_setup(void) +{ +#ifdef RDC_DISABLED + NOTICE("RDC off \n"); +#else + struct imx_rdc_regs *imx_rdc = (struct imx_rdc_regs *)IMX_RDC_BASE; + + NOTICE("RDC imx_rdc_set_masters default \n"); + imx_rdc_set_masters_default(); + + /* + * Need to substact offset 0x40000000 from CPU address when + * programming rdc region for i.mx8mq. + */ + +#ifdef DECRYPTED_BUFFER_START + /* Domain 2 no write access to memory region below decrypted video */ + /* Prevent VPU to decode outside secure decoded buffer */ + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[2].mrsa), 0); + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[2].mrea), DECRYPTED_BUFFER_START - IMX_DDR_BASE); + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[2].mrc), 0xC00000AF); +#endif // DECRYPTED_BUFFER_START + +#ifdef DECRYPTED_BUFFER_END + NOTICE("RDC setup memory_region[0] decrypted buffer DID0 W DID2 R/W\n"); + /* Domain 0 memory region W decrypted video */ + /* Domain 2 memory region R decrypted video */ + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[0].mrsa), DECRYPTED_BUFFER_START - IMX_DDR_BASE); + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[0].mrea), DECRYPTED_BUFFER_END - IMX_DDR_BASE); + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[0].mrc), 0xC0000061); +#endif // DECRYPTED_BUFFER_END + +#ifdef DECODED_BUFFER_END + NOTICE("RDC setup memory_region[1] decoded buffer DID2 R/W DID3 R/W\n"); + /* Domain 1+2 memory region R/W decoded video */ + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[1].mrsa), DECODED_BUFFER_START - IMX_DDR_BASE); + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[1].mrea), DECODED_BUFFER_END - IMX_DDR_BASE); + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[1].mrc), 0xC000003D); + + /* Domain 1+2+3 no access to memory region above decoded video */ + /* Only CPU in secure mode can access TEE memory region (cf TZASC configuration) */ + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[3].mrsa), DECODED_BUFFER_END - IMX_DDR_BASE); + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[3].mrea), 0xC0000000 - IMX_DDR_BASE); + mmio_write_32((uintptr_t)&(imx_rdc->mem_region[3].mrc), 0xC0000003); +#endif // DECODED_BUFFER_END + +#endif // RDC_DISABLED +} + /* get SPSR for BL33 entry */ static uint32_t get_spsr_for_bl33_entry(void) { @@ -103,7 +167,7 @@ void bl31_tzc380_setup(void) if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) return; - NOTICE("Configureing TZASC380\n"); + NOTICE("Configuring TZASC380\n"); tzc380_init(IMX_TZASC_BASE); @@ -230,8 +294,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl32_image_ep_info.spsr = 0; /* Pass TEE base and size to uboot */ bl33_image_ep_info.args.arg1 = 0xBE000000; + /* TEE size + RDC reserved memory = 0x2000000 + 0x2000000 + 0x30000000 */ +#ifdef DECRYPTED_BUFFER_START + bl33_image_ep_info.args.arg2 = 0xC0000000 - DECRYPTED_BUFFER_START; +#else bl33_image_ep_info.args.arg2 = 0x2000000; #endif +#endif + bl31_tzc380_setup(); /* Assign M4 to domain 1 */ @@ -243,6 +313,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, csu_test(); rdc_test(); #endif + + bl31_imx_rdc_setup(); + } void bl31_plat_arch_setup(void) diff --git a/plat/imx/imx8mm/platform.mk b/plat/imx/imx8mm/platform.mk index 30052bcc..702b3bb0 100644 --- a/plat/imx/imx8mm/platform.mk +++ b/plat/imx/imx8mm/platform.mk @@ -53,3 +53,19 @@ A53_DISABLE_NON_TEMPORAL_HINT := 0 ERRATA_A53_835769 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 + +ifneq (${DECRYPTED_BUFFER_START},) +$(eval $(call add_define,DECRYPTED_BUFFER_START)) + +ifneq (${DECRYPTED_BUFFER_LEN},) +$(eval $(call add_define,DECRYPTED_BUFFER_LEN)) +endif +endif + +ifneq (${DECODED_BUFFER_START},) +$(eval $(call add_define,DECODED_BUFFER_START)) + +ifneq (${DECODED_BUFFER_LEN},) +$(eval $(call add_define,DECODED_BUFFER_LEN)) +endif +endif |