diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-09-17 15:48:06 +0800 |
|---|---|---|
| committer | Bai Ping <ping.bai@nxp.com> | 2018-09-17 15:54:10 +0800 |
| commit | 7a50e0e390349738b8987b49cc05edeadaeaddbc (patch) | |
| tree | 1d4b9e13e0d878a043dd1468876a4ff14a5fee4b /plat/imx/imx8mq/imx8mq_bl31_setup.c | |
| parent | 7b60954d68e074d6d0d1a6f828f4392cf7c7137d (diff) | |
plat: imx8mq: add 100us delay after USB OTG SRC bit 0 clear
After the SRC bit clear, we must wait for a while to make sure
the operation is finished.
for USB OTG, the limitations are:
1. before system clock configuration. ipg clock runs at 12.5MHz.
delay time should longer than 82us.
2. after system clock configuration. ipg clock runs at 66.5MHz.
delay time should longer than 15.3us.
so add udelay 100 to safely clear the SRC bit 0.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'plat/imx/imx8mq/imx8mq_bl31_setup.c')
| -rw-r--r-- | plat/imx/imx8mq/imx8mq_bl31_setup.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/plat/imx/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8mq/imx8mq_bl31_setup.c index 55289400..5fc21a56 100644 --- a/plat/imx/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8mq/imx8mq_bl31_setup.c @@ -12,6 +12,7 @@ #include <context.h> #include <context_mgmt.h> #include <debug.h> +#include <generic_delay_timer.h> #include <stdbool.h> #include <mmio.h> #include <platform.h> @@ -281,6 +282,8 @@ void bl31_plat_arch_setup(void) void bl31_platform_setup(void) { + generic_delay_timer_init(); + /* init the GICv3 cpu and distributor interface */ plat_gic_driver_init(); plat_gic_init(); |